Abstract: An apparatus and method of communicating signals between a 2.5 volt internal circuit and both 3.3 and 5 volt external circuits using a P-well. The apparatus includes a circuit having a P-well control circuit and a number of NMOS transistors. The P-well control circuit is configured to receive a P-well control signal and an external signal, and in accordance therewith selectively generate a P-well voltage. The NMOS transistors are coupled to the P-well control circuit. At least one of the NMOS transistors has a bulk region configured to receive the P-well voltage. The NMOS transistors are further configured to receive a 5 volt signal and in accordance therewith selectively generate a 2.5 volt signal. The NMOS transistors are still further configured to receive a 3.3 volt signal and in accordance therewith selectively generate a 2.5 volt signal.

Abstract: A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.

Abstract: A circuit including a ferroelectric capacitor can be used to store the value of nodes of volatile logic elements in a logic circuit. In this manner, the state of a complex logic circuit, such as a CPU or an I/O device, can be stored in the non-volatile ferroelectric capacitors. After an accidental or planned power outage, the non-volatile ferroelectric capacitors can be used to restore the values of the nodes. Additionally, a planned power loss can be save system power in circuits that are power consumption sensitive.