Abstract: Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A cascode stage is configured to selectively couple an output pad to a reference terminal. An ESD sensor may detect a change in voltage indicative of an ESD event occurring at the output pad, causing a gate drive to turn on the cascode stage to conduct ESD current in response to detection of the ESD event at the output pad. A leakage blocker is also included to prevent leakage current from the cascode stage to the gate drive while there is not an ESD event.

Abstract: In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode material feature (330) located adjacent a gate width (w) side of the gate electrode (320). The semiconductor device (300) may further include a silicide region (350) located over the substrate (310) proximate a side of the gate electrode (320), the gate electrode material feature (330) breaking the silicided region (350) into multiple silicide portions (353, 355, 358).

Abstract: In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.