Patents by Inventor Denis Amparo
Denis Amparo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230380302Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.Type: ApplicationFiled: July 24, 2023Publication date: November 23, 2023Inventors: Daniel Yohannes, Denis Amparo, Oleksandr Chernyashevskyy, Oleg Mukhanov, Mario Renzullo, Andrei Talalaeskii, Igor Vernik, John Vivalda, Jason Walter
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Patent number: 11711985Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.Type: GrantFiled: September 13, 2021Date of Patent: July 25, 2023Assignee: SeeQC IncInventors: Daniel Yohannes, Denis Amparo, Oleksandr Chernyashevskyy, Oleg Mukhanov, Mario Renzullo, Andrei Talalaevskii, Igor Vernik, John Vivalda, Jason Walter
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Publication number: 20210408355Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Inventors: Daniel Yohannes, Denis Amparo, Oleksandr Chernyashevskyy, Oleg Mukhanov, Mario Renzullo, Andrei Talalaeskii, Igor Vernik, John Vivalda, Jason Walter
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Patent number: 11121302Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.Type: GrantFiled: October 11, 2019Date of Patent: September 14, 2021Inventors: Daniel Yohannes, Denis Amparo, Oleksandr Chernyashevskyy, Oleg Mukhanov, Mario Renzullo, Andrei Talalaeskii, Igor Vernik, John Vivalda, Jason Walter
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Patent number: 10833243Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.Type: GrantFiled: August 17, 2017Date of Patent: November 10, 2020Assignee: SeeQC Inc.Inventors: Sergey K. Tolpygo, Denis Amparo, Richard Hunt, John Vivalda, Daniel Yohannes
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Publication number: 20200119251Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.Type: ApplicationFiled: October 11, 2019Publication date: April 16, 2020Inventors: Daniel Yohannes, Denis Amparo, Oleksandr Chernyashevskyy, Oleg Mukhanov, Mario Renzullo, Andrei Talalaeskii, Igor Vernik, John Vivalda, Jason Walter
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Patent number: 10505097Abstract: A superconducting circuit is disclosed for fast digital readout of on-chip diagnostics in an array of devices in an integrated circuit. The digital readout comprises a digital RSFQ multiplexer to select the readout channel. This permits a large number of devices to be tested with a minimum of input and output lines. The devices may comprise digital devices (such as elementary RSFQ cells), or analog devices (such as inductors, resistors, or Josephson junctions) with a SQUID quantizer to generate a digital signal. The diagnostic array and the digital multiplexer are preferably configured to operate as part of the same integrated circuit at cryogenic temperatures.Type: GrantFiled: March 4, 2019Date of Patent: December 10, 2019Assignee: Hypres, Inc.Inventors: Amol Inamdar, Jie Ren, Denis Amparo
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Patent number: 10222416Abstract: A superconducting circuit is disclosed for fast digital readout of on-chip diagnostics in an array of devices in an integrated circuit. The digital readout comprises a digital RSFQ multiplexer to select the readout channel. This permits a large number of devices to be tested with a minimum of input and output lines. The devices may comprise digital devices (such as elementary RSFQ cells), or analog devices (such as inductors, resistors, or Josephson junctions) with a SQUID quantizer to generate a digital signal. The diagnostic array and the digital multiplexer are preferably configured to operate as part of the same integrated circuit at cryogenic temperatures.Type: GrantFiled: April 13, 2016Date of Patent: March 5, 2019Assignee: Hypres, Inc.Inventors: Amol Inamdar, Jie Ren, Denis Amparo
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Patent number: 9741920Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.Type: GrantFiled: September 3, 2015Date of Patent: August 22, 2017Assignee: Hypres, Inc.Inventors: Sergey K. Tolpygo, Denis Amparo, Richard Hunt, John Vivalda, Daniel Yohannes
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Patent number: 9130116Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.Type: GrantFiled: May 6, 2013Date of Patent: September 8, 2015Assignee: Hypres Inc.Inventors: Sergey K. Tolpygo, Denis Amparo, Richard Hunt, John Vivalda, Daniel Yohannes
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Patent number: 8437818Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.Type: GrantFiled: October 28, 2012Date of Patent: May 7, 2013Assignee: Hypres, Inc.Inventors: Sergey K. Tolpygo, Denis Amparo, Richard Hunt, John Vivalda, Daniel Yohannes
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Patent number: 8301214Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.Type: GrantFiled: January 7, 2011Date of Patent: October 30, 2012Assignee: Hypres, Inc.Inventors: Sergey K. Tolpygo, Denis Amparo, Richard Hunt, John Vivalda, Daniel Yohannes