Patents by Inventor Denis Baylor
Denis Baylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250181549Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: ApplicationFiled: November 13, 2024Publication date: June 5, 2025Inventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Patent number: 12174780Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: GrantFiled: March 30, 2023Date of Patent: December 24, 2024Assignee: Google LLCInventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Patent number: 12032511Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: GrantFiled: June 21, 2022Date of Patent: July 9, 2024Assignee: Google LLCInventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Publication number: 20230237007Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: ApplicationFiled: March 30, 2023Publication date: July 27, 2023Inventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Publication number: 20220391347Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: ApplicationFiled: June 21, 2022Publication date: December 8, 2022Inventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Patent number: 11372801Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: GrantFiled: June 11, 2021Date of Patent: June 28, 2022Assignee: Google LLCInventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Publication number: 20210303506Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: Michial Allen Gunter, Denis Baylor, Clifford Biffle, Charles Ross
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Patent number: 8954905Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.Type: GrantFiled: October 14, 2013Date of Patent: February 10, 2015Assignee: Cadence Design Systems, Inc.Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
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Patent number: 8694931Abstract: In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a second portion of the integrated circuit design; wherein the second memory space is independent of the first memory space.Type: GrantFiled: February 20, 2011Date of Patent: April 8, 2014Assignee: Cadence Design Systems, Inc.Inventor: Denis Baylor
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Patent number: 8560984Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.Type: GrantFiled: January 24, 2012Date of Patent: October 15, 2013Assignee: Cadence Design Systems, Inc.Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
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Patent number: 8386978Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.Type: GrantFiled: February 14, 2012Date of Patent: February 26, 2013Assignee: Cadence Design Systems, Inc.Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
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Patent number: 8375350Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.Type: GrantFiled: November 21, 2011Date of Patent: February 12, 2013Assignee: Cadence Design Systems, Inc.Inventors: Sascha Richter, Denis Baylor
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Patent number: 8127260Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.Type: GrantFiled: December 1, 2006Date of Patent: February 28, 2012Assignee: Cadence Design Systems, Inc.Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
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Patent number: 8065640Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.Type: GrantFiled: May 30, 2007Date of Patent: November 22, 2011Assignee: Cadence Design Systems, Inc.Inventors: Sascha Richter, Denis Baylor
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Patent number: 7913194Abstract: In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a second portion of the integrated circuit design; wherein the second memory space is independent of the first memory space.Type: GrantFiled: May 31, 2007Date of Patent: March 22, 2011Assignee: Cadence Design Systems, Inc.Inventor: Denis Baylor