Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A digital-to-analog converter includes an array of capacitors, an array of capacitor switches, positive and negative high-bandwidth reference buffers, positive and negative low-bandwidth reference buffers, and a reference-voltage-selection switch. Each capacitor switch electrically couples a respective capacitor to either a positive or a negative reference voltage line. The reference-voltage-selection switch electrically couples the positive and negative reference voltage lines to either positive and negative high-bandwidth voltages or to positive and negative low-bandwidth voltages. The positive and negative high-bandwidth voltages are produced by the positive and negative high-bandwidth reference buffers. The positive and negative low-bandwidth voltages are produced by the positive and negative low-bandwidth reference buffers.

Abstract: A time-interleaved sampling system includes an input signal having a time-varying analog value and a plurality of samplers. Each sampler is operable in a hold mode and a track mode. In the track mode, the samplers track the analog value of the input signal. In the hold mode, each sampler holds a respective analog value of the input signal that a respective sampler tracked immediately before entering the hold mode. The samplers enter the track mode in a predetermined sequence. After a last sampler in the predetermined sequence enters the track mode, the predetermined sequence is repeated in a loop. At random intervals, a skipped sampler in the predetermined sequence is bypassed from entering the track mode.

Abstract: A digital-to-analog converter includes an array of capacitors, an array of capacitor switches, positive and negative high-bandwidth reference buffers, positive and negative low-bandwidth reference buffers, and a reference-voltage-selection switch. Each capacitor switch electrically couples a respective capacitor to either a positive or a negative reference voltage line. The reference-voltage-selection switch electrically couples the positive and negative reference voltage lines to either positive and negative high-bandwidth voltages or to positive and negative low-bandwidth voltages. The positive and negative high-bandwidth voltages are produced by the positive and negative high-bandwidth reference buffers. The positive and negative low-bandwidth voltages are produced by the positive and negative low-bandwidth reference buffers.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A time-interleaved sampling system includes an input signal having a time-varying analog value and a plurality of samplers. Each sampler is operable in a hold mode and a track mode. In the track mode, the samplers track the analog value of the input signal. In the hold mode, each sampler holds a respective analog value of the input signal that a respective sampler tracked immediately before entering the hold mode. The samplers enter the track mode in a predetermined sequence. After a last sampler in the predetermined sequence enters the track mode, the predetermined sequence is repeated in a loop. At random intervals, a skipped sampler in the predetermined sequence is bypassed from entering the track mode.

Abstract: A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function.

Abstract: A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function.