Patents by Inventor Denis Crespo

Denis Crespo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8804289
    Abstract: A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 12, 2014
    Assignee: NXP, B.V.
    Inventors: Denis Crespo, Herve Marie, Nguyen Trieu Luan Le, Mickael Lucas
  • Publication number: 20120032703
    Abstract: A shrinking-pulse digital delay line (400) has a cascade of a plurality of stages (102,104) for modifying a width of a pulse propagating down the cascade (106 to 118). Each specific one of the stages has an input (106,116), an output (108,118) and a main path (110,112,120,122) between the input and the output. The main path has a first inverter (110,120) and a second inverter (112,122) connected in series via an intermediate node (114,124). Each specific stage has a third inverter (128,140) connected between the input and the intermediate node of a downstream stage in the cascade (102,104); and also has a fourth inverter (132,144) connected between the intermediate node of the specific stage (mode 114, stage 102, mode 124, stage 104) and the output (118, stage 104) of the downstream stage (stage 104).
    Type: Application
    Filed: February 16, 2010
    Publication date: February 9, 2012
    Applicant: NXP B.V.
    Inventors: Denis Crespo, Yves Dufour, Herve Marie
  • Publication number: 20100214706
    Abstract: A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal.
    Type: Application
    Filed: October 13, 2008
    Publication date: August 26, 2010
    Applicant: NXP B.V.
    Inventors: Denis Crespo, Herve Marie, Nguyen Trieu Luan Le, Mickael Lucas