Abstract: A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply switching circuit for applying a current to at least one selected bit line; a word line address decoder for selecting a word line; and a program control logic circuit for blowing the semi-fusible links in the memory cells identified by the intersection of the selected word and bit lines; a method is disclosed of testing programmed and unprogrammed read only memory.

Abstract: A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply switching circuit for applying a current to at least one selected bit line; a word line address decoder for selecting a word line; and a program control logic circuit for blowing the semi-fusible links in the memory cells identified by the intersection of the selected word and bit lines; a method is disclosed of testing programmed and unprogrammed read only memory.

Abstract: A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.

Abstract: An electronic programmable read-only-memory (EPROM) is provided having a field effect transistor with the gate electrode thereof coupled to a capacitor adapted to store charge produced in a channel region of the transistor in response to a logic state programming voltage applied between one of the source and drain regions and the gate electrode. The field effect transistor and the capacitor are formed in a common semiconductor body along with CMOS transistors. The field effect transistor has relatively heavy doped source and drain regions separated by an oppositely doped channel region. A gate electrode is disposed over the channel region. Lightly doped regions, having the same conductivity type as the source and drain regions, extend laterally from the source and drain regions to peripheral regions of the channel region to suppress generation of “hot” electrons in the transistor and the CMOS transistors.