Patents by Inventor Denis Dutey
Denis Dutey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797306Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.Type: GrantFiled: April 26, 2022Date of Patent: October 24, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: Gregory Trunde, Denis Dutey
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Patent number: 11436162Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: GrantFiled: May 22, 2020Date of Patent: September 6, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Patent number: 11416022Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.Type: GrantFiled: May 20, 2020Date of Patent: August 16, 2022Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Stephane Martin, Denis Dutey
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Publication number: 20220253315Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Inventors: Gregory Trunde, Denis Dutey
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Patent number: 11314513Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.Type: GrantFiled: March 24, 2021Date of Patent: April 26, 2022Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Gregory Trunde, Denis Dutey
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Publication number: 20210318873Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.Type: ApplicationFiled: March 24, 2021Publication date: October 14, 2021Inventors: Gregory Trunde, Denis Dutey
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Patent number: 11055173Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: December 4, 2019Date of Patent: July 6, 2021Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20200379924Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Publication number: 20200379506Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.Type: ApplicationFiled: May 20, 2020Publication date: December 3, 2020Inventors: Stephane Martin, Denis Dutey
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Publication number: 20200110663Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om RANJAN, Riccardo GEMELLI, Denis DUTEY
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Patent number: 10528422Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: November 13, 2017Date of Patent: January 7, 2020Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20190146868Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: November 13, 2017Publication date: May 16, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Patent number: 8923408Abstract: A method of transcoding a sub-picture unit each comprising encoded sub-picture pixel data including sub-picture lines separated into at least a first field and a second field as well as a set of display control commands associated with the sub-picture pixel data, comprises the step of pre-processing (53) the display control commands to prepare transcoding to frame format. Encoded lines of said top and bottom fields are then merged (56,73) into a single encoded frame and the display control commands are modified (56,74) according to changes in encoded sub-picture pixel data before outputting.Type: GrantFiled: November 5, 2003Date of Patent: December 30, 2014Assignee: STMicroelectronics SAInventors: Denis Dutey, Nikola Cornij
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Publication number: 20040146111Abstract: A method of transcoding a sub-picture unit each comprising encoded sub-picture pixel data including sub-picture lines separated into at least a first field and a second field as well as a set of display control commands associated with the sub-picture pixel data, comprises the step of pre-processing (53) the display control commands to prepare transcoding to frame format. Encoded lines of said top and bottom fields are then merged (56,73) into a single encoded frame and the display control commands are modified (56,74) according to changes in encoded sub-picture pixel data before outputting.Type: ApplicationFiled: November 5, 2003Publication date: July 29, 2004Applicant: STMICROELECTRONICS SAInventors: Denis Dutey, Nikola Cornij
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Patent number: 6205180Abstract: A device for demultiplexing data encoded according to a MPEG standard in the form of a data flow including system and picture packets. The device includes means for independently organizing, according to the nature (system packet, video packet, audio packet, etc.) of the data included in the packets, the storing of the data in various registers, some of the registers being accessible in read mode by a RAM and other registers being accessible by a microprocessor.Type: GrantFiled: December 26, 1996Date of Patent: March 20, 2001Assignee: SGS-Thomson Microelectronics S.A.Inventor: Denis Dutey
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Patent number: 5255316Abstract: Digital-type hands-free telephone apparatus is provided including a microcontroller, an audio board and a COFIDEC circuit, in which the microcontroller permanently calculates the average values of 16 successive samples on each one of the send and receive channels and deduces therefrom which channel is to be enabled while attenuating the other using tables provided in ROM memory.Type: GrantFiled: July 31, 1991Date of Patent: October 19, 1993Assignee: Alcatel N.V.Inventors: Jean-Pierre Poirier, Francois Bonneau, Denis Dutey