Abstract: The present disclosure relates to a network chip (108) comprising: a programmable infrastructure (201) having a plurality of access points (202); at least one chiplet communications interface (3D PLUG) suitable for interfacing with at least one chiplet (110), each chiplet communications interface (3D PLUG) being coupled to a corresponding one of the access points (202); and a plurality of network-to-network communications interfaces (206, 208, 210, 212) each suitable for interfacing with another network chip (108).

Abstract: This method for executing a request to exchange data, between first and second disjoint physical addressing spaces controlled by first and second distinct circuits for first and second respective software processes, comprises the creation of a communication channel between these two circuits. It further comprises sending, by the first process, of said request to exchange data, this request designates a virtual address in a virtual addressing space of the second process, and execution of the request to exchange data between the disjoint physical addressing spaces of the two processes, without invoking a processor executing the second process. During creation of the channel, a translation of the virtual addressing space of the second process into its physical addressing space is created and associated with this channel in the second circuit. During execution of the request, data for identification of the channel is added to the virtual address designated in the request.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: Circuitry for providing an output video signal from a portable device to an external display, the circuitry including a processor block with an image processor, and a video encoder block with a video encoder for providing the output video signal to the external display, the processor block and the video encoder block being connected to each other by a serial interface arranged to provide image date from the processor block to the video encoder, the serial interface having at least one data lane and at least one first clock lane, wherein the video encoder block includes a first input connected to the at least one data lane for receiving image data and a second input connected to the at least one first clock lane for receiving a first clock signal, and wherein at least one of the video encoder block and the processor block has a third input arranged to receive a control signal for controlling data flow over the serial interface.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.