Abstract: A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.

Abstract: The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The method comprises the initial step of raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a sufficient value to cause to start FN tunnelling through the oxide of the transistor. A new structure particularly suitable for this method is also disclosed.

Abstract: A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.