Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

Abstract: A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Abstract: In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.

Abstract: A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Abstract: A system includes a mobile phone configured to create an inverted signal having characteristics inverse to identified noise components of a detected audio signal. The mobile phone is configured to provide the inverted signal as an output to a headphone, such that a combination of the identified noise components and the inverted signal substantially cancel each other out.

Abstract: In certain systems, local request's require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request, is present If the associated information is present, a request is placed in an output request queue to service the local request If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison.

Abstract: Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.

Abstract: A command queueing apparatus for directing address and command information amongst the various interfaces, or consumers, on a multi-CPU node in a computer system. The apparatus includes a core queue containing core queue entries, each core queue entry corresponding to a pending system bus operation. Each core queue entry includes one or more consumer information fields specific to each consumer. Also included is a plurality of virtual queues, each virtual queue corresponding to a consumer, each virtual queue having a virtual queue entry. A virtual queue entry for a consumer is a subset of the fields of a core queue entry, the subset of fields including the consumer information fields for the consumer corresponding to the virtual queue.