Abstract: A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Abstract: A multi-adaptive processor element architecture incorporating a field programmable gate array (“FPGA”) control element having at least one embedded processor core and a pair of user FPGAs forming a user array is disclosed in conjunction with high volume dynamic random access memory (“DRAM”) and dual-ported static random access memory (“SRAM”) banks. In operation, the DRAM is “read” using its fast sequential burst modes and the lower capacity SRAM banks are then randomly loaded allowing the user FPGAs to experience very high random access data rates from what appears to be a very large virtual SRAM. The reverse also happens when the user FPGAs are “writing” data to the SRAM banks. These overall control functions may be managed by an on-chip DMA engine that is implemented in the control FPGA.