Abstract: A method is provided for dramatically improving communications data throughput on embedded systems and reducing the load on the operating system and central processing unit by moving the network protocol logic nearer to the underlying communication hardware, and utilizing the communication processor hardware abstraction layer (CPHAL) concepts. This movement of the network protocol logic allows leveraging the CPHAL data structures, which are tightly bound to the communication packets being processed. The decision making is made just above the CPHAL layer; and the CPHAL data structure is preserved. Copying data is avoided by manipulating of pointers within the CPHAL buffer.

Abstract: A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Abstract: A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom.

Abstract: A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first root physical device to an internal CBA bus segment of one or more remote external physical device includes the first root physical device having a first serial communications interface module in the root device coupled between said internal CBA bus segment and an input and output port of the root device for serializing bus transactions from the first device to the output port of the root device and deserializing data received from at the input port to the internal CBA bus segment of the first device. The remote external physical device includes a second serial communications interface module coupled between the internal CBA bus segment and an input and output port of the remote device for serializing bus transactions from the remote device to the output port of the remote device and deserializing data received at the input port to the internal CBA bus segment of said remote device.

Abstract: A method of providing an operating system independent interface between an operating system (OS) and a communications processor media access control MAC (CPMAC) is provided that includes providing a communications processor Hardware Abstraction Layer (CPHAL) between the OS and a driver with the driver communicating to said CPHAL layer which communicates with the communications hardware processor media access control MAC. The operating system passes information to the CPHAL and the CPHAL at a later time returning the information and wherein said CPHAL passes information to the OS in the same way. The Communications Processor Hardware Abstraction Layer (CPHAL) comprises hooks so that the OS-specific coding is embedded into said CPHAL. The start-up initialization between CPHAL and the OS includes providing a protocol that allows the CPHAL to pass details of its feature set and allows CPHAL to retrieve information from the OS.

Abstract: A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first root physical device to an internal CBA bus segment of one or more remote external physical device includes the first root physical device having a first serial communications interface module in the root device coupled between said internal CBA bus segment and an input and output port of the root device for serializing bus transactions from the first device to the output port of the root device and deserializing data received from at the input port to the internal CBA bus segment of the first device. The remote external physical device includes a second serial communications interface module coupled between the internal CBA bus segment and an input and output port of the remote device for serializing bus transactions from the remote device to the output port of the remote device and deserializing data received at the input port to the internal CBA bus segment of said remote device.

Abstract: A serial communications interface is described that enables the extension of an internal Communications Bus Achitecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: An improved communications system with a circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution is provided. More particularly, the system has a first memory, a plurality of protocol handlers, a bus connected to said protocol handlers, a second memory connected to said bus, and a memory controller connected to said bus and said second memory for selectively comparing addresses, transferring data between said protocol handlers and said second memory, and transferring data between said second memory and said first memory. A first embodiment is a local area network controller having a first circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution, and an address lookup circuit interconnected to said first circuit.

Abstract: The present invention includes a method and system for routing broadcast packets in a network (250) using a switching device (200) which is operable to interconnect sub-portions (202, 204) of the network (250). Each network (250) sub-portion (202, 204) is connected to at least one of a plurality of switch ports (232, 236, 240, 244) on the switching device (200). The switching device (200) is further operable to forward certain ones of the broadcast packets between the sub-portions (202, 204) of the network (250) via the switch ports (232, 236, 240, 244) in accordance with a forwarding algorithm and to forward all other of the broadcast packets to a processor (320). The processor (320) is communicatively connected to the switching device (200) and is operable to forward the other ones of the broadcast packets in accordance with a set of pre-defined broadcast routing heuristics.

Abstract: A communications system with a circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution and includes a first memory, a plurality of protocol handlers, a bus connected to the protocol handlers, a second memory connected to the bus and a memory controller connected to the bus and the second memory for selectively comparing addresses, transferring data between the protocol handlers and the second memory, and transferring data between the second memory and the first memory. A first embodiment is a local area network controller having a first circuit with a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution, and an address lookup circuit interconnected with the first circuit.

Abstract: A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom.

Abstract: A local area network ("LAN") controller operable in an IEEE 802.3u network and an IEEE 802.12 network. A common physical connector is used for both standards, attached to an attachment medium such as a card. An 802.3u circuit is attached to the card, implementing the following 802.3u functions: A media access controller ("MAC") layer, and a physical media independent ("PMI") layer that provides the IEEE 802.3u media independent interface ("MII"). An 802.12 circuit is also attached to the card, implementing the following IEEE 802.12 functions: An LLC layer, an MAC layer, and a PMI layer, providing an MII to a device implementing an 802.12 physical media dependent ("PMD") layer. A circuit coupled to the 802.12 circuit multiplexes, according to a predetermined strategy, 802.12 PMI to PMD signals over the physical connector and, alternatively, communicates 802.3u MII signals between the 802.3u circuit and the physical connector.

Abstract: A communications network adapter of the type coupling a computer, in which the computer includes a microprocessor, main memory and a system bus, that controls host interrupts in a manner to improve system performance. The adapter includes a buffer memory for storing data to be transferred between the bus an the network, and a transfer controller that controls the transfer of data between the main memory and the buffer memory and between the network and the buffer memory. The adapter also includes an interrupt controller that monitors predetermined events relating to data transfer between the computer and the network, and that causes the sending of interrupt signals to the microprocessor. Interrupt signals cause the microprocessor to initiate processing associated with the transfer of data between the computer and the network.

Abstract: A communications processor system 10b that permits communications task code to be safely downloaded from a host system. Direct access to local memory 15b of the communications processor system 10b is permitted only during a downloading process while system 10b in a reset state. This downloading process is implemented with a special control register. In user mode, the system 10b controls access to local memory 15b by downloaded task code. Specifically, access is prohibited with respect to privileged memory areas, and is limited to a relatively small predetermined range of addresses with respect to other memory areas. This memory protection process is implemented with a special status register and a number of mapping registers.

Abstract: The present invention includes a data transfer system (28) which includes a first bus (32) and a second bus (34) wherein both buses are bidirectionally connected to a first memory (30). Similarly, a third bus (42) and a fourth bus (44) are bidirectionally connected to a second memory (40). A plurality of data cells (50a through 50h) are provided for intermediate storage when units of information are transferred between first and second memories (30 and 40). A first pointer (37) is under control of first pointer circuit (36) and first control circuit (38) such that buses (32 and 34) may have access to selected ones of the plurality of data cells (50a through 50h). Similarly, a second pointer (47) is under control of second pointer circuit (46) and second control circuit (48) such that third and fourth buses (42 and 44) may have access to the plurality of data cells (50a through 50h).