Abstract: The present description concerns an electronic device having an antenna configured to receive a radio frequency signal. The electronic device further includes a control unit. The control unit is off, and the antenna receives a radio frequency signal. The antenna is configured to deliver a first voltage representative of the radio frequency signal to power the control unit with the voltage for the duration of the booting of the control unit.

Abstract: Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the output bus (18), a second counter (28) preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to the width of the input bus (14), the decrementation of the second counter being started at the same time as the decrementation of the first counter by a start counter signal (38), and a threshold unit (52) for determining the minimum threshold from the contents of the second counter when the first counter has reached zero and providing the minimum threshold to a buffer management logic unit a buffer management logic unit (22) providing write grant signals when data may be read from the data buffer and sent to an output device.

Abstract: A drift compensation system includes a first clock phase alignment circuit adapted for providing an output clock signal which is frequency locked to an input reference clock signal; a second clock phase alignment circuit identical to the first clock phase alignment circuit but wherein the reference clock signal is the output clock signal provided by the first clock phase alignment circuit; first deviation means at the output of the first clock phase alignment circuit for providing a first deviation between its current clock phase and its initial clock phase; second deviation means at the output of the second clock phase alignment circuit for providing a second deviation between its current clock phase and its initial clock phase; and a phase control logic adapted for providing first phase shift signals as inputs to the first clock phase alignment circuit in order to cancel the phase shift between the output clock signal and the reference clock signal in response to the difference between the first and the sec

Abstract: A system for connecting a receiver to a redundant power supply. The power supply units are connected to the receiver by means of a pair of control switches, each being connected in series between one of the power units and the receiver, and each having its intrinsic diode forwardly biased between the power unit and the receiver. A voltage comparator senses which of the power supply units is having the higher potential difference between its high and low potential terminals. The output of the comparator controls the gate of both control switches such that the control switch in series with the sensed power supply unit is conducting while the other one is off. When a reversed polarity is applied to the receiver, the receiver is protected by the intrinsic diode. When at least one of the power supplies is connected with the correct polarity, the receiver is supplied without an appreciable voltage drop and with the lowest possible power losses.

Abstract: A drift compensation system includes a first clock phase alignment circuit adapted for providing an output clock signal which is frequency locked to an input reference clock signal; a second clock phase alignment circuit identical to the first clock phase alignment circuit but wherein the reference clock signal is the output clock signal provided by the first clock phase alignment circuit; first deviation means at the output of the first clock phase alignment circuit for providing a first deviation between its current clock phase and its initial clock phase; second deviation means at the output of the second clock phase alignment circuit for providing a second deviation between its current clock phase and its initial clock phase; and a phase control logic adapted for providing first phase shift signals as inputs to the first clock phase alignment circuit in order to cancel the phase shift between the output clock signal and the reference clock signal in response to the difference between the first and the sec

Abstract: Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the output bus (18), a second counter (28) preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to the width of the input bus (14), the decrementation of the second counter being started at the same time as the decrementation of the first counter by a start counter signal (38), and a threshold unit (52) for determining the minimum threshold from the contents of the second counter when the first counter has reached zero and providing the minimum threshold to a buffer management logic unit a buffer management logic unit (22) providing write grant signals when data may be read from the data buffer and sent to an output device.

Abstract: A system for controlling the connection of a receiving device to a main or a redundant power supply is provided. The system typically comprises a power supply voltage comparator, a reference voltage detector and a polarity detector to determine error voltage conditions from the main or from the redundant power supply. A decision circuit generates thereby a control signal to allow the connection of the receiver device to the appropriate power supply through the activation of a switch device.

Abstract: A system for connecting a receiver to a redundant power supply. The power supply units are connected to the receiver by means of a pair of control switches, each being connected in series between one of the power units and the receiver, and each having its intrinsic diode forwardly biased between the power unit and the receiver. A voltage comparator senses which of the power supply units is having the higher potential difference between its high and low potential terminals. The output of the comparator controls the gate of both control switches such that the control switch in series with the sensed power supply unit is conducting while the other one is off. When a reversed polarity is applied to the receiver, the receiver is protected by the intrinsic diode. When at least one of the power supplies is connected with the correct polarity, the receiver is supplied without an appreciable voltage drop and with the lowest possible power losses.