Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.

Abstract: In one embodiment, an image processor is configured to obtain phase images, and to group the phase images into pseudoframes with each of at least a subset of the pseudoframes comprising multiple ones of the phase images and having as a first phase image thereof one of the phase images that is not a first phase image of an associated depth frame. A velocity field is estimated by comparing corresponding phase images in respective ones of the pseudoframes. Phase images of one or more pseudoframes are modified based at least in part on the estimated velocity field, and one or more depth images are generated based at least in part on the modified phase images. By way of example, different groupings of the phase images into pseudoframes may be used for each obtained phase image, allowing depth images to be generated at much higher rates than would otherwise be possible.

Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement an object tracking module. The object tracking module is configured to obtain one or more images, to extract contours of at least two objects in at least one of the images, to select respective subsets of points of the contours for the at least two objects based at least in part on curvatures of the respective contours, to calculate features of the subsets of points of the contours for the at least two objects, to detect intersection of the at least two objects in a given image, and to track the at least two objects in the given image based at least in part on the calculated features responsive to detecting intersection of the at least two objects in the given image.

Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a face recognition system utilizing the image processing circuitry and the memory, the face recognition system comprising a face recognition module. The face recognition module is configured to identify a region of interest in each of two or more images, to extract a three-dimensional representation of a head from each of the identified regions of interest, to transform the three-dimensional representations of the head into respective two-dimensional grids, to apply temporal smoothing to the two-dimensional grids to obtain a smoothed two-dimensional grid, and to recognize a face based on a comparison of the smoothed two-dimensional grid and one or more face patterns.

Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a contour classification module. The contour classification module is configured to identify one or more hand poses from one or more isolated regions in a first image, to determine a contour of a given one of the one or more hand poses, to calculate one or more features of the contour of the given hand pose, to identify one or more isolated regions in a second image, and to determine whether at least a portion of one or more isolated regions in the second image matches the given hand pose based on a comparison of one or more points characterizing the portion of the one or more isolated regions in the second image and the one or more features of the contour of the given hand pose.

Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system comprises a finger detection and tracking module configured to identify a hand region of interest in a given image, to extract a contour of the hand region of interest, to detect fingertip positions using the extracted contour, and to track movement of the fingertip positions over multiple images including the given image.

Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to obtain a vocabulary of hand poses, to estimate a plurality of hand features based on the hand region of interest, the plurality of hand features comprising a first set of features estimated from the hand region of interest and a second set of features comprising at least one feature estimated using a transform on a contour of the hand region of interest, and to recognize a static pose of the hand region of interest based on the first set of features and the second set of features, wherein respective numbers of features in the first set of features and the second set of features are based at least in part on a size of the vocabulary of hand poses.

Abstract: The disclosure is directed to a system and method of image processing. According to various embodiments of the disclosure, a storage module in communication with a plurality of memory banks stores a plurality of pixels of an image in the memory banks and interleaves the memory banks to enable a plurality of image scanners to access the plurality of pixels. A scanning module scans a selection of pixels in at least four directions relative to a first pixel of the plurality of pixels utilizing the plurality of image scanners. A singular points detection module in communication with the scanning module acquires a depth of each pixel of the selection of scanned pixels and determines a singularity value of the first pixel by comparing the depth of the first pixel with the depth of each pixel of the selection of pixels.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.

Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.

Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.

Abstract: A machine-based method for modifying a parity-check matrix in a manner that controllably and quantifiably raises the corresponding error-floor level and/or rate of miscorrection to make these quantities observable in direct read-channel simulations that can be completed in a relatively short amount of time. In one embodiment, the method is used to compare different turbo-decoding schemes by comparing the read-channel performance characteristics corresponding to a modified matrix, instead of the original parity-check matrix. In another embodiment, the method is used to validate a heuristic error-rate estimation tool. After being validated, the heuristic error-rate estimation tool can advantageously be used to obtain, in a relatively short amount of time, relatively accurate estimates of the error rates corresponding to the original parity-check matrix.

Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.

Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.

Abstract: In one embodiment, a heterogeneous multi-processor computer system includes (i) a plurality of dedicated processors (DPs), each DP configured to implement one or more program modules during runtime operations; (ii) two or more control processors (CPs), each CP configured to run scheduling software for controlling the runtime operations by a corresponding subset of DPs; and (iii) one or more buses interconnecting the DPs and CPs. Each CP is configured to vary timing of implementation of the program modules for the corresponding subset of DPs based on resource availability, and each CP is configured to vary timing of data transfers by the corresponding subset of DPs based on resource availability.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors. The system comprising a plurality of processors of two or more different processor types. Machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution. A Source Code Generator (SCG) integrates scheduling information for the selected schedule solution into the scheduling software for a first processor such that the scheduling information is compiled with the scheduling software.