Abstract: Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Abstract: Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.