Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit. The BIST emulator includes a function that initializes a plurality of indicators associated with respective data storage locations in communication with the integrated circuit in response to the operator level instruction.

Abstract: Various approaches for simulating a circuit design are described. In one approach, charge-holding combinations of connected circuit components in a non-hierarchical representation of a circuit design are identified as known circuit components. Each identification is made as a function of characterized responses of the combinations. Identification information of the known circuit components is stored in association with the identified charge-holding combinations. For each of the identified charge-holding combinations, sub-combinations of circuit components therein that implement a known circuit are identified, and identification information of the known circuits is stored in association with the identified sub-combinations. Hierarchical relationships between the identified charge-holding combination and each sub-combination of the charge-holding combination are identified and data describing the hierarchical relationships is stored.

Abstract: One example embodiment of an approach to circuit design simulation involves simulating a circuit design. Access to a circuit design block is provided for a plurality of simulation tools. A run status associated with the circuit design block is updated in response to the block being simulated by one of the plurality of simulation tools. In response to a first simulation tool request for access to information regarding a circuit design block, a run status of the block is checked, the run status being indicative of the block being simulated. The block is simulated as a function of the run status, and results of the simulation are returned to the simulation tool making the first simulation tool request.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit. The BIST emulator includes a function that enables an assert operation of a plurality of data storage locations in communication with the integrated circuit in response to the operator level instruction.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Abstract: Various embodiments of a system, method and database for storing circuit element classification information in a relational database are disclosed. One database embodiment comprises a block relation, a structure relation, a FET relation, a NET relation and an association relation.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit. The BIST emulator includes a function that that directs a data value stored in a data storage location to an output device.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit. The BIST emulator includes a function that initializes a plurality of data storage locations in communication with the integrated circuit.

Abstract: An example embodiment of an approach to circuit design simulation involves runtime configuration of a circuit design simulator. The circuit design simulator is configured with initial configuration parameter values. The configured circuit design simulator is used to simulate a circuit design, with results of the simulation being stored. When runtime configuration parameter values are updated during the simulation, the circuit design simulator is reconfigured with the runtime configuration parameter values. The circuit design simulation is continued with the runtime configuration parameter values, and results of the continuing simulation are stored.

Abstract: One embodiment of a method comprises retrieving test data corresponding to test results from a plurality of fuses, each one of the plurality of fuses residing on a different one of a plurality of semiconductor devices and each one of the plurality of fuses having a common location on the semiconductor devices, determining from the test data which of the plurality of fuses are defective fuses, and specifying on an output report the common location of the determined defective fuses when a number of the defective fuses are at least equal to a predefined portion of the plurality of fuses.

Abstract: A system for automatically routing power in an integrated circuit, the system comprising memory for storing data defining a representation of an integrated circuit having a power contact and a power connection, and logic configured to analyze the data and to automatically route power from the power connection to the power contact.

Abstract: One example embodiment of property data storage includes using row and column names to identify properties to a particular circuit design component. Each of a plurality of columns in a relational database table is named with a property name indicative of a respective one of a plurality of circuit design properties. Another column in the relational database table is named with a property name indicating the column is unassigned to a circuit design property. Rows in the relational database table are named with respective names of the plurality of design components. When a circuit design component has a property indicated by one of the property names of the columns, a data value indicative of the circuit design component having the property is stored in the table entry at the column having the one of the property names and at the row having the name of the circuit design component.

Abstract: One example embodiment of an approach to circuit design analysis comprises partitioning a circuit design into first, second and boundary parts, the boundary part including circuit portions from each of the first part and second part at a boundary between the first part and second part. The first, second and boundary parts are independently simulated to generate a respective first, second and third set of result data that are combined to create a result for the design.

Abstract: According to an example embodiment of an approach to circuit design processing involves using an interface for retrieving and processing circuit design data for use by a plurality of simulation tools. The interface includes an application program callable function configured to return functional classification data in response to an application programming interface (API) call from a simulation tool. The API call specifies a design block identifier that is used by the application program callable function to search a data source for functional classification data associated with the design block identifier. If functional classification data associated with the design block identifier is not found in the data source, a plurality of circuit elements associated with the design block identifier is retrieved from a netlist.

Abstract: One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period of time for a second plurality of storage elements; determining a plurality of attributes for each of the first storage elements and the second storage elements based upon the test results, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determining a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generating an output report indicating at least two of the attribute statistics of the first storage elements and the second storage elements.

Abstract: Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor mounted thereto, the heat sink comprising an internal chamber that is adapted to receive a fluid flow that removes heat from the heat sink. In one embodiment, a method for dissipating heat generated by a processor comprises forcing fluid through an internal chamber formed within a heat sink to which the processor is mounted, forcing the fluid from the internal chamber of the heat sink through at least one hollow prong that extends from the heat sink and that is in fluid communication with the internal chamber of the heat sink, and forcing fluid over exterior surfaces of the at least one hollow prong.

Abstract: One example embodiment of an interface arrangement for retrieving circuit design data comprises a first application program callable function configured to, in response to an application programming interface (API) call to the first function that specifies a block, read design data related to the block in a first format and store the design data in a second format different from the first. The interface arrangement further comprises a second application program callable function configured to, in response to an API call to the second function requesting block characteristics from the design data stored in the second format, access the stored design data in the second format and return information regarding characteristics of the specified block.

Abstract: One embodiment of a method comprises retrieving test data corresponding to test results from a plurality of fuses, each one of the plurality of fuses residing on a different one of a plurality of semiconductor devices and each one of the plurality of fuses having a common location on the semiconductor devices, determining from the test data which of the plurality of fuses are defective fuses, and specifying on an output report the common location of the determined defective fuses when a number of the defective fuses are at least equal to a predefined portion of the plurality of fuses.

Abstract: Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor, the heat sink forming part of an enclosed interior passage, and at least one prong extending from the heat sink and positioned within the interior passage, wherein the enclosed interior passage is adapted to receive fluid forced through the interior passage. In one embodiment, a method for dissipating heat generated by a processor comprises forming an interior passage in part with a heat sink to which the processor is mounted, and forcing the fluid through the interior passage and over prongs contained within the interior passage and extending from the heat sink.