Patents by Inventor Denise Thienpont

Denise Thienpont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Encapsulated chip scale package having flip-chip on lead frame structure
    Patent number: 7656048
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: February 2, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joseph K. Fauty, James P. Letterman, Jr., Denise Thienpont
  • Encapsulated chip scale package having flip-chip on lead frame structure and method
    Patent number: 7439100
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Joseph K. Fauty, James P. Letterman, Jr., Denise Thienpont
  • ENCAPSULATED CHIP SCALE PACKAGE HAVING FLIP-CHIP ON LEAD FRAME STRUCTURE AND METHOD
    Publication number: 20080197459
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Application
    Filed: April 22, 2008
    Publication date: August 21, 2008
    Inventors: Joseph K. Fauty, James P. Letterman, Denise Thienpont
  • Encapsulated chip scale package having flip-chip on lead frame structure and method
    Publication number: 20070040283
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Inventors: Joseph Fauty, James Letterman, Denise Thienpont