Patents by Inventor Deniz E. Civay
Deniz E. Civay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10552567Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).Type: GrantFiled: January 17, 2018Date of Patent: February 4, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Deniz E. Civay, Elise Laffosse
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Publication number: 20190220567Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).Type: ApplicationFiled: January 17, 2018Publication date: July 18, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Deniz E. Civay, Elise Laffosse
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Patent number: 10186524Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: March 5, 2018Date of Patent: January 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
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Publication number: 20180197882Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: David PRITCHARD, Lixia LEI, Deniz E. CIVAY, Scott D. LUNING, Neha NAYYAR
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Patent number: 9941301Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: December 22, 2016Date of Patent: April 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
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Patent number: 9754829Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: September 5, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Erik R. Hosler, Deniz E. Civay
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Patent number: 9748176Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: August 29, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Deniz E. Civay, Erik R. Hosler
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Patent number: 9704807Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Deniz E. Civay, Erik R. Hosler
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Publication number: 20170140985Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: Erik R. Hosler, Deniz E. Civay
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Publication number: 20170141036Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: Deniz E. Civay, Erik R. Hosler
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Publication number: 20170141027Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: Erik R. Hosler, Deniz E. Civay
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Publication number: 20170141035Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: Deniz E. Civay, Erik R. Hosler
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Patent number: 9633942Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Erik R. Hosler, Deniz E. Civay
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Patent number: 9397012Abstract: A method includes forming a first plurality of instances of a first pattern on a substrate. The first pattern includes a plurality of features defining a first spacing between features in a first direction. The instances in the first plurality are offset from one another at least in a second direction other than the first direction. The substrate is cleaved along a cleavage line. At least a first critical dimension of a feature in the first plurality of instances intersected by the cleavage line is measured.Type: GrantFiled: June 27, 2014Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Deniz E. Civay, Ralph Schlief
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Publication number: 20150380320Abstract: A method includes forming a first plurality of instances of a first pattern on a substrate. The first pattern includes a plurality of features defining a first spacing between features in a first direction. The instances in the first plurality are offset from one another at least in a second direction other than the first direction. The substrate is cleaved along a cleavage line. At least a first critical dimension of a feature in the first plurality of instances intersected by the cleavage line is measured.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Deniz E. Civay, Ralph Schlief