Abstract: An example includes a method for producing a multipixel detector, the method including: providing a bottom layer including a first and a second bottom electrode, depositing an electrically insulating layer on the bottom layer, forming a first opening through the electrically insulating layer, depositing a first photon absorbing material in the first opening, forming a second opening through the electrically insulating layer, depositing a second photon absorbing material in the second opening, planarizing the deposited electrically insulating layer, the first photon absorbing material, and the second photon absorbing material to form a flat surface, and forming a common top electrode on top of the flat surface.

Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed.

Abstract: A method is provided for producing different patterns on a single substrate. The method includes executing at least twice a sequence of the following steps: depositing a hardmask on the layer of interest and patterning the hardmask with a predefined pattern to create an accessible portion on the layer of interest; spinning a glass/carbon layer on the hardmask and on the accessible portion of the layer of interest; spin coating a block copolymer on the glass/carbon layer; transferring a predefined block copolymer pattern onto the layer of interest thereby obtaining a transferred pattern, removing the hard mask; filling the transferred pattern followed by chemical mechanical polishing or etching back, wherein different block copolymer patterns are used.

Abstract: The disclosure relates to a method for processing a laser device, for example a III-V on silicon laser, including: providing a carrier substrate; forming a grating structure on the carrier substrate, wherein the grating structure delimits a cavity on a surface of the carrier substrate; placing a die in the cavity and bonding the die to the carrier substrate, wherein the die comprises an active region including a III-V semiconductor material; transferring the die from the carrier substrate to a silicon substrate by bonding an exposed side of the die to the silicon substrate and subsequently debonding the carrier substrate from the die; and forming a photonic structure, for example a silicon waveguide, coupled to the die.

Abstract: A Microelectromechanical Systems (MEMS) device combining a MEMS layer and a Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit (IC), and its fabrication method is provided. The fabrication method includes: processing the MEMS layer on a first semiconductor substrate, the MEMS layer including one or more movable structures and one or more anchor structures; processing one or more first contacts on the first semiconductor substrate, each first contact being processed into one of the anchor structures and being configured to bias that anchor structure; processing the CMOS IC on a second semiconductor substrate; processing one or more second contacts on the second semiconductor substrate, each second contact being connected to the CMOS IC; and bonding the first semiconductor substrate to the second semiconductor substrate such that each first contact directly contacts one of the second contacts. The method can allow fabricating the MEMS device without vapor HF etching.

Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.

Abstract: A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.

Abstract: A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Abstract: A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed.

Abstract: A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Abstract: Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

Abstract: Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

Abstract: A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Abstract: A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase.