Abstract: A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

Abstract: A high speed full adder circuit is shown to include logic circuitry responsive to the levels of the two digital signals to be added for: (a) immediately producing an appropriate carry signal when the levels of the digital signals are the same; and (b) inverting the carry signal into such adder when the levels of the digital signals differ.

Abstract: A subtractor for an N-bit digital number comprising N cascaded cells, each cell being adapted to effect subtraction by two's complement arithmetic and to provide a carry-out signal in accordance with the level of two bits being processed and a carry-in signal.