Abstract: A digital signal regenerator, arranged for fault locating, receives a sequence of four-level signals representing first and second sequences of binary signals. When fault locating, the second sequence of binary signals is the same as the first sequence of binary signals but is delayed by n time slots. The received sequence of four-level signals is decoded into the first and second sequences of binary signals. Once decoded, the first sequence of binary signals is delayed by n time slots into a delayed first sequence of binary signals. The delayed first sequence of binary signals and the second sequence of binary signals are compared with each other. The comparator produces an error signal only when concurrent bits of the delayed first sequence of binary signals and of the second sequence of binary signals are different from one another.

Abstract: A digital transmission line fault location signal generator includes a maximal length linear feedback shift register having m stages for generating a first pseudorandom sequence of binary signals with a period 2.sup.m -1. The first pseudorandom sequence of binary signals is delayed by n time slots into a second pseudorandom sequence of binary signals. A circuit merges the first and second pseudorandom sequences of binary signals into a combined sequence of signals on the digital transmission line.

Abstract: A fault location system includes a test code generator located at an end terminal for transmitting a test code sequence of signals onto a digital transmission line. A line regenerator located along the transmission line detects the test code sequence of signals. Other circuitry interconnected with the line regenerator determines and stores a number count indicating how many errors are detected in the test code sequence. In response to a polling request from a fault location circuit in the end terminal, the other circuitry storing the count indicating errors transmits that count to a fault location circuit which calculates an error rate therefrom.