Abstract: The disclosed embodiments provide a system that facilitates transmission of a serial data stream. The system may include, in a receiver of the serial data stream, a first mechanism for converting from single-ended signaling to differential signaling, wherein the first mechanism facilitates rejection of common mode noise in the serial data stream. For example, the first mechanism may be a balun and/or a common-mode choke.

Abstract: The disclosed embodiments provide a system that facilitates transmission of a serial data stream. The system may include, in a receiver of the serial data stream, a first mechanism for converting from single-ended signaling to differential signaling, wherein the first mechanism facilitates rejection of common mode noise in the serial data stream. For example, the first mechanism may be a balun and/or a common-mode choke.

Abstract: A system including power savings modes, the system including a processor that supports bus semantics in its hardware for a power state of a first level, wherein the first level is lowest power level the processor is able to enter, a system core logic module coupled to the processor, and a memory, coupled to the system core logic module, storing instructions, which when executed by the system, causes the system core logic to be notified of an impending processor idle state that is compatible with the latency required for system core logic power savings modes and wherein, in response to being notified of an impending processor idle state, the system core logic implements thread, core, or package level power saving idle modes lower than supported by the first level based on a latency hierarchy and independent of normal power saving bus semantics.

Abstract: A system including power savings modes, the system including a processor that supports bus semantics in its hardware for a power state of a first level, wherein the first level is lowest power level the processor is able to enter, a system core logic module coupled to the processor, and a memory, coupled to the system core logic module, storing instructions, which when executed by the system, causes the system core logic to be notified of an impending processor idle state that is compatible with the latency required for system core logic power savings modes and wherein, in response to being notified of an impending processor idle state, the system core logic implements thread, core, or package level power saving idle modes lower than supported by the first level based on a latency hierarchy and independent of normal power saving bus semantics.

Abstract: Integrated access cover arrangements for use in a portable computing devices, where the portable computing devices include a processor and are configured to house a user accessible component are presented including: a base configured to be coupled to the portable computing device; an integrated access cover housing a keyboard, the integrated access cover being slidingly connected with the base and configured to be disposed in at least a closed position and an open position with respect to the base, the user accessible component being hidden from a user when the integrated access cover is disposed in the closed position, the user accessible component being accessible by the user when the integrated access cover is disposed in the open position. In some embodiments, arrangements further include: a drive mechanism for translating the integrated access cover. Advantages include the ability to utilize lower profile configurations while maintaining functionality.

Abstract: High-speed bipolar signals transmitted along standard twisted pair telephone wiring are subject to InterSymbol Interference which is corrected by an equalizer circuit that is operably responsive to predetermined parameters of bipolar signals detected at the secondary of a line transformer. These parameters are input to a control logic circuit which includes several stages, each producing a set of past dependent logical control signals which are input to corresponding equalizer tap circuits having outputs connected to a common output bus. Each tap circuit includes an integrator that is incrementally charged and discharged by an electronically switched capacitor. A tap weight voltage output from each integrator is subsequently summed directly or inversely by a second switched capacitor under control of the logical input signals.