Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.

Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A system for coupling a local area network to a wide area network utilizes a PCI (Peripheral Component Interface) bus to couple a PCI interface to a PCI network interface card, which is coupled to the wide area network. The wide area network could be an asynchronous transfer mode network or a high bandwidth ethernet. If the PCI network interface card operates as a PCI master, then the PCI interface will operate as a PCI slave. If the PCI network interface card operates as a PCI slave, then the PCI interface of the invention will operate as a PCI master.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A memory interface for multi-port access to a memory unit, such as a static random-access memory (SRAM) device. The memory interface, which is generally adapted for a local area network (LAN) forwarding engine, provides single port read/write access to SRAM device, and arbitrates requests from the access interfaces to allocate bandwidth of the SRAM device among the requests. One embodiment allocates at least 50% of the bandwidth to a peripheral component interface (PCI) bus target interface and a PCI bus master interface, collectively. The arbitration logic may include a plurality of bandwidth control registers associated with respective access interfaces used to determine a permitted amount of bandwidth that an access interface is to have, wherein a request from an access interface is masked based on a value in its associated bandwidth control register. Arbitration can further allocate bandwidth using time division multiplexing.