Abstract: An overload current limiting circuit includes an output control circuit responsive to a logic input signal for generating a control signal for driving an output device to produce at an output terminal a signal representative of the logic input signal; and a sense circuit for sensing voltage at the output terminal indicative of a current overload and diverting a portion of that current to change the control signal to the output device to limit the overload current.

Abstract: A multi-channel integrated circuit comprises a plurality of channels (CH1 to CH20). A DAC (3) is provided in each channel (CH1 to CH20) for converting digital data inputted to the circuit (1) through an I/O port (14). Digital data to be converted by the DACs (3) is selectively applied to input registers (10) of each channel (CH1 to CH20) on a digital data bus (16) under the control of an interface and control logic circuit (15). The digital words written to the input registers (10) are in turn written to DAC registers (9) through corresponding digital switches (12) for conversion by the DACs (3). A clear code register (22) stores a clear code for writing to the DAC registers (9) in response to a clear signal applied to a clear terminal (24) of the circuit (1) so that analogue outputs appearing on output terminals (5) of the channels (CH1 to CH20) are of a predetermined value, typically, zero volts, when the circuit (1) is set in a clear condition.

Abstract: A multi-channel integrated circuit comprises a plurality of channels (CH1 to CH20). A DAC (3) is provided in each channel (CH1 to CH20) for converting digital data inputted to the circuit (1) through an I/O port (14). Digital data to be converted by the DACs (3) is selectively applied to input registers (10) of each channel (CH1 to CH20) on a digital data bus (16) under the control of an interface and control logic circuit (15). The digital words written to the input registers (10) are in turn written to DAC registers (9) through corresponding digital switches (12) for conversion by the DACs (3). A clear code register (22) stores a clear code for writing to the DAC registers (9) in response to a clear signal applied to a clear terminal (24) of the circuit (1) so that analogue outputs appearing on output terminals (5) of the channels (CH1 to CH20) are of a predetermined value, typically, zero volts, when the circuit (1) is set in a clear condition.

Abstract: An overload current limiting circuit includes an output control circuit responsive to a logic input signal for generating a control signal for driving an output device to produce at an output terminal a signal representative of the logic input signal; and a sense circuit for sensing voltage at the output terminal indicative of a current overload and diverting a portion of that current to change the control signal to the output device to limit the overload current.