Abstract: High density time division busses suffer from many problems, one of which is that impedance discontinuities cause signal reflections to occur along the bus. These reflections, in turn, affect the settling time and noise margins of the bus and thus reduce the time "window" in which valid signals may be received. There is disclosed a transmission bus structure which allows for bidirectional, multi-port operation by using current drivers instead of the traditional voltage drivers for placing data signals on the bus. The transmission bus is designed in a manner which allows transmission and reception from a single clock on the same clock edge thereby substantially increasing the time allowed for transmission response and also simplifying the clock distribution requirements.

Abstract: The disclosed signal limiting circuit is bridged on to a bidirectional communication path (T, R) and functions to selectively attenuate excessive signals (2V.sub.A) being transmitted in a predetermined direction on the bidirectional communication path. This is accomplished by a signal discriminator circuit (100) which separates the excessive signal (2V.sub.A) from the plurality of signals appearing on the communication path (T, R). The signal discriminator circuit (100) also inverts the isolated excessive signal, passes it through an attenuator (102) to a signal injection circuit (103) which injects a controlled amount of the 180 degrees out-of-phase isolated excessive signal back on the communication path (T, R) to cancel out a portion of the excessive signal, thereby providing selective attenuation of the excessive signal.