Patents by Inventor Dennis Blankenship

Dennis Blankenship has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7872936
    Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventor: Dennis Blankenship
  • Publication number: 20100070696
    Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Inventor: Dennis Blankenship
  • Publication number: 20070264971
    Abstract: A method for selecting an active router in a communication device includes providing multiple routers in the device, coupling the routers to a single physical link, monitoring a status for each of the routers, and selecting one of the routers as an active router by positioning its corresponding relay.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 15, 2007
    Applicant: Cisco Technology, Inc.
    Inventors: Dennis Blankenship, Michael Otto, Peter Beal, John Glotzer
  • Publication number: 20070140284
    Abstract: A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet handle, interface handle, and data packet are communicated to a second processor. A plurality of data packets that are destined for the same output are multiplexed. At least one packet handle, one interface handle, and the multiplexed data packet are communicated to the first processor, and the multiplexed data packet is output.
    Type: Application
    Filed: February 19, 2007
    Publication date: June 21, 2007
    Applicant: Cisco Technology, Inc.
    Inventors: Dennis Blankenship, Glenn Preslar, Thomas Scheviak
  • Patent number: 6157990
    Abstract: A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: December 5, 2000
    Assignee: Mitsubishi Electronics America Inc.
    Inventors: William L. Randolph, Dennis Blankenship, Rhonda Cassada
  • Patent number: 5838606
    Abstract: A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: November 17, 1998
    Assignee: Mitsubishi Semiconductor America, Inc.
    Inventors: Dennis Blankenship, Stephen Mann
  • Patent number: 5798972
    Abstract: An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: August 25, 1998
    Assignee: Mitsubishi Semiconductor America, Inc.
    Inventors: Tim Lao, Dennis Blankenship, Rhonda Cassada
  • Patent number: 5784329
    Abstract: The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: July 21, 1998
    Assignee: Mitsubishi Semiconductor America, Inc.
    Inventors: Dennis Blankenship, Tim Lao, Rhonda Cassada