Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

Abstract: Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

Abstract: A circuit and method for clipping input integers to a specified range comprising the steps of providing a mask wherein a bit is set for each out-of-range bit and not set for in-range bits and applying the mask to input integers so that any integers outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. Other systems and methods are disclosed.

Abstract: The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between a quad precision representation and a two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further include hardware for performing arithmetic operations on double-extended precision quantities.

Abstract: A multi-chip module includes a mechanically floated substrate on which integrated circuit devices are mounted. The substrate is located within a heat exchanger. In one embodiment, a spring or an array of springs biases the substrate upwardly to press the integrated circuit devices against a surface within the heat exchanger. The substrate is displaceable with respect to the heat exchanger, allowing accommodations to differences in thermal expansion coefficients and to non-uniformities resulting from less than exact manufacturing tolerances of the substrate, the heat exchanger and the integrated circuit devices. Another embodiment includes resting the substrate on a conformable membrane that is used to entrap a fixed volume of thermally-conductive liquid. The membrane-and-liquid arrangement mechanically floats the substrate and ensures a proper integrated circuit device/exchanger thermal interface.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Abstract: A multi-chip module having a conformal heat transfer interface to adapt to variations in the height and angle of integrated circuit chips and to achieve a thermal energy path between each chip and a heat sink. The conformal heat transfer interface includes a deformable metallic membrane and a liquid under pressure. The liquid has a high thermal conductivity and provides a pressure for deforming the metallic membrane to compensate for non-coplanarity of the chips. The module integrates the structural support, RF shielding, contamination-protection elements, and the heat-dissipating mechanism that are desired in the design of multi-chip modules. Double-sided cooling of the module significantly improves the thermal characteristics of a module, even in the absence of the conformal heat transfer interface.