Patents by Inventor Dennis BURIANEK

Dennis BURIANEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444027
    Abstract: A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 13, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Mordechai Rothschild, Sumanth Kaushik, Melissa A. Smith, Livia Racz, Dennis Burianek
  • Publication number: 20200365512
    Abstract: A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Inventors: Mordechai ROTHSCHILD, Sumanth KAUSHIK, Melissa A. SMITH, Livia RACZ, Dennis BURIANEK