Abstract: An apparatus for calibrating a test unit adapted to characterize CML integrated circuits. The apparatus is adapted to deskew the time delays of each pin of the fixture which receives the CML circuit under test with respect to a certain predetermined pin and preselected pin thereof. The preselected pin and a predetermined pin are shorted and the time delay between the generation of a shaped pulse and its connection through the preselected pin to the predetermined pin and to a test unit is determined by said test unit. The time delays are then utilized to remove any time delays caused by the test apparatus itself so that the CML circuit under test can be accurately characterized.

Abstract: A testing apparatus for CML integrated circuits having a power splitter connected at its input to a pulse generator, and at one output to a test unit and at its other output to the CML circuit through a matrix. The output waveform of the CML circuit is provided through the matrix to the test unit.