Abstract: A back EMF signal from PWM driven motor is passed through an attenuation circuit. The attenuation circuit has a first mode of operation and a second mode of operation. The first mode of operation, used to sample a higher voltage back EMF signal during PWM on-time, applies the back EMF signal to a resistive divider formed of a first resistor and second resistor connected in series. The second mode of operation, used to sample a lower voltage back EMF signal during PWM off-time, applies the back EMF signal to a circuit comprised of a transistor conduction path in series with the second resistor. A control signal, responsive PWM on-time and off-time state, controls switching between the first and second modes.

Abstract: A back EMF signal from PWM driven motor is passed through an attenuation circuit. The attenuation circuit has a first mode of operation and a second mode of operation. The first mode of operation, used to sample a higher voltage back EMF signal during PWM on-time, applies the back EMF signal to a resistive divider formed of a first resistor and second resistor connected in series. The second mode of operation, used to sample a lower voltage back EMF signal during PWM off-time, applies the back EMF signal to a circuit comprised of a transistor conduction path in series with the second resistor. A control signal, responsive PWM on-time and off-time state, controls switching between the first and second modes.

Abstract: Moderately accurate closed loop speed control of a universal motor is attained without the need for any type of speed sensor. Motor armature (across the brushes) voltage is sensed and supplied to a control circuit for processing along with sensed motor current and zero-crossing information. Integration of the motor armature voltage provides a value which is related to current motor speed. By adjusting the gating angle for triac actuation, the armature voltage integral can be maintained at a desired value associated with a desired motor speed. The sensed motor current is also integrated to provide a speed droop compensation value that is added to the desired value, and the gating angle for triac actuation is adjusted to move the armature voltage integral value to approach the summed value of the speed droop compensation value and desired value.

Abstract: Moderately accurate closed loop speed control of a universal motor is attained without the need for any type of speed sensor. Motor armature (across the brushes) voltage is sensed and supplied to a control circuit for processing along with sensed motor current and zero-crossing information. Integration of the motor armature voltage provides a value which is related to current motor speed. By adjusting the gating angle for triac actuation, the armature voltage integral can be maintained at a desired value associated with a desired motor speed. The sensed motor current is also integrated to provide a speed droop compensation value that is added to the desired value, and the gating angle for triac actuation is adjusted to move the armature voltage integral value to approach the summed value of the speed droop compensation value and desired value.

Abstract: A system and method of advancing the commutation sequence of a brushless DC motor is provided. The motor having a plurality of coils, each of the coils coupled together at one end to a common center tap and coupled at an opposite end, through a respective coil tap, to both a source voltage and ground via selectively actuateable switches having diodes coupled in parallel therewith. The motor operates in a pulse width modulation (PWM) mode having PWM-on states and PWM-off states. During PWM-off states, a coil tap voltage from the coil tap of a floating phase is provided to a preconditioning circuit. The preconditioning circuit adjusts the floating phase coil tap voltage to compensate for an amount of voltage substantially equal to an amount of voltage by which a voltage at the center tap deviates from zero. The preconditioning circuit further includes sharpening circuitry for amplifying the adjusted floating phase coil tap voltage.

Abstract: A system and method of advancing the commutation sequence of a brushless DC motor is provided. The motor having a plurality of coils, each of the coils coupled together at one end to a common center tap and coupled at an opposite end, through a respective coil tap, to both a source voltage and ground via selectively actuateable switches having diodes coupled in parallel therewith. The motor operates in a pulse width modulation (PWM) mode having PWM-on states and PWM-off states. During PWM-off states, a coil tap voltage from the coil tap of a floating phase is provided to a preconditioning circuit. The preconditioning circuit adjusts the floating phase coil tap voltage to compensate for an amount of voltage substantially equal to an amount of voltage by which a voltage at the center tap deviates from zero. The preconditioning circuit further includes sharpening circuitry for amplifying the adjusted floating phase coil tap voltage.

Abstract: A permanent magnet brushless DC motor controller, and method of operation of the controller, provide effective and smooth regulation of the speed of the motor from zero to above base speed (e.g. at least about 100% above base speed). For a three phase motor the controller comprises three Hall sensors, a power amplifier comprising a plurality of power electronic switch connected to the motor, two switches (bottom and top) for each phase, and at least an eight bit microprocessor connected to and controlling the switches, and a frequency to voltage controller. The Hall sensors are connected substantially directly to the microprocessor, and also through the frequency to voltage converter. In response to sensing by the Hall sensors, both directly and through the frequency to voltage converter, the microprocessor is used to control the electronic switches to smoothly speed regulate the motor both below and above base speed.

Abstract: A ripple rejection filter for removing the fundamental frequency of load voltage from control signals in closed-loop phase controlled systems operating from an AC power source. A low-pass filter is connected in parallel with a firing point synchronized sample and hold and high-pass filter series combination. The output of the low-pass and high-pass filters are combined to produce a resulting signal representative of an input signal but with ripple rejected.

Abstract: A method and apparatus for digital phase synchronization to an AC power line is disclosed, having an analog-to-digital conversion providing a digital phase error signal which is processed by an inverting proportional plus integral transfer function and compared to a digital timer to determine the time for the next analog-to-digital conversion.

Abstract: A method and apparatus for operating a DC motor controller according to a first gain when the armature current of the DC motor is discontinuous, according to a second gain when the armature current is continuous, and according to a third gain when the armature current is in transition from the discontinuous to continuous conduction. The gains have proportional and integral terms and the integral term in the discontinuous and transition regions varies inversely to a current reference in the controller.

Abstract: A method for operating a DC motor controller according to a first gain when the armature current of the DC motor is discontinuous, according to a second gain when the armature current is continuous, and according to a third gain when the armature current is in transition from the discontinuous to continuous conduction. The gains have proportional and integral terms and the integral term in the discontinuous and transition regions varies inversely to a current reference in the controller.

Abstract: An overload detection circuit protects a motor against currents above rated current that persist for certain exposure times. The allowable exposure times are inversely related to the degree of overload current. The circuit has two overload current sensors with two respective overload thresholds. These are both connected to a pulse generating circuit and the pulse rate is accelerated when the second overload threshold is reached. The pulse generating circuit couples pulses to a pair of cascaded counters which generate a fault signal when a predetermined count is reached. The pulse generating circuit includes an integrator with a capacitor that must be discharged, before another pulse can be generated. The pulse generating circuit includes a comparator which operates a switch to discharge the capacitor shortly before coupling each pulse to the counters, to prevent a delay that would otherwise occur between signals from the integrator circuit.

Abstract: Ramp generating circuits, for synchronizing SCR firing control signals to the phase-varying signals derived from a three-phase AC power source, each have a compensating circuit connected across an operational amplifier and a capacitor to control the peak value of the ramp signal generated at the output of the operational amplifier. The compensating circuit maintains the peak value of the ramp signal close to its calculated value despite variations in the actual value of the capacitor from its nominal or rated value and despite changes in power line frequency between 50 hertz and 60 hertz. The compensating circuit includes a T-section passive network, a voltage-following amplifier and several feedback resistors connected from the output of the operational amplifier to its inverting (-) input. This compensating circuit increases or decreases charging current to the capacitor according to the type of compensation that is necessary.