Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: An approach for routing over a radio network is provided. A terminal receives a packet over the radio network, which supports meshed connectivity, wherein the packet is destined for a destination host. The terminal determines whether the destination host is reachable by a communication interface based upon a route table, and selectively redirects the packet over the radio network according to the route table. A route server is provided to collect routes from the terminal as well as other terminals within the radio network. The route server then disseminates the collect routes to the terminals for updating of their respective route tables. The present invention has particular applicability to a fully meshed satellite network.

Abstract: According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.

Abstract: Disclosed is an integrated circuit chip test apparatus that has a module test fixture having contact pads that are adapted to make contact with signal input/output pins on an integrated circuit chip being tested. An intermediate banking box is connected to the module text fixture and a tester is connected to the intermediate banking box. The tester includes at least one bank of channels there are more pins on the integrated circuit chip than there are channels in the tester. The intermediate banking box includes switches that are connected between the contact pads and the channels. The switches are adapted to selectively connect a subset of the contact pads to the channels to connect the tester to a subset of pins, thereby allowing the tester to test a portion of the integrated circuit that corresponds to the subset of pins.

Abstract: An approach for routing over a radio network is provided. A terminal receives a packet over the radio network, which supports meshed connectivity, wherein the packet is destined for a destination host. The terminal determines whether the destination host is reachable by a communication interface based upon a route table, and selectively redirects the packet over the radio network according to the route table. A route server is provided to collect routes from the terminal as well as other terminals within the radio network. The route server then disseminates the collect routes to the terminals for updating of their respective route tables. The present invention has particular applicability to a fully meshed satellite network.

Abstract: A satellite wide area communications network (10) includes a remote transmitter/receiver (28A) that is coupled through a modem unit (30A) to multiple card readers (12A-1 to 12A-n). A master transmitter/receiver (26) is satellite linked to the remote transmitter/receiver and is coupled through a central packet network (16) to multiple host computers (18-1 to 18-j). A network host computer address is determined for each transaction card inserted in the card readers, and the network address is processed to establish a direct link to the host computer for the card through the modem unit, the satellite link (22A, 20, 24), and the central packet network.