Abstract: An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom contacts on the bottom surface configured to interface with a component beneath the interposer, through connections between corresponding top and bottom contacts and a plurality of signal probe points on the edge surface. The interposer may include an electrical pathway connecting a first through connection to a first signal probe point. The electrical pathway may contact the first through connection at a first intersection. A resistor may be disposed along the electrical pathway, between the first intersection and the first signal probe point. The electrical pathway from the first intersection to the resistor may be an unconditioned signal pathway. The electrical pathway from the resistor to the first signal contact may be a conditioned signal pathway. The unconditioned signal pathway may have a length of not greater than 0.20 inch.

Abstract: An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom contacts on the bottom surface configured to interface with a component beneath the interposer, through connections between corresponding top and bottom contacts and a plurality of signal probe points on the edge surface. The interposer may include an electrical pathway connecting a first through connection to a first signal probe point. The electrical pathway may contact the first through connection at a first intersection. A resistor may be disposed along the electrical pathway, between the first intersection and the first signal probe point. The electrical pathway from the first intersection to the resistor may be an unconditioned signal pathway. The electrical pathway from the resistor to the first signal contact may be a conditioned signal pathway. The unconditioned signal pathway may have a length of not greater than 0.20 inch.

Abstract: An interposer is shown with contact points on a lateral edge. When assembled between a board under test and an integrated circuit, traces of the interposer carry signals between the board under test and the integrated circuit and also between signal lines of the integrated circuit and the lateral edge contact points. The signals can then be accessed by test equipment at the lateral edge contact points. The interposer may include additional components connected to the traces.

Abstract: A test assembly that may provide access to signals of a circuit that includes an integrated circuit. The test assembly may include structural members that limit movement of components relative to each other.

Abstract: A component interposer provides access to signals communicated between an integrated circuit and control circuit board. The component interposer may include a signal circuit board and a socket. The board may include one or more electrical contacts that may be used to sample a signal. The socket may include first and second portions. The first portion may include a surface that contacts with the control circuit board. The first portion may have a first width and first length. The second portion may have a surface that contacts the signal board. The second portion may have a second width and second length. The first length may be smaller than the second length, the first width may be smaller than the second width, or both. The socket may include an overhang that defines a space or void. The socket may include one or more pins for aligning the signal board and the socket. The component interposer may include one or more fasteners.

Abstract: A bridge connector assembly may provide access to signals of a circuit that includes an integrated circuit. The bridge connector assembly may include first and second circuit boards that are mated edge to edge, structural members that maintain the position of each circuit board in relation to each other and connectors to carry signals from edge connectors on one board to corresponding connectors on the second board.

Abstract: A test assembly that may provide access to signals of a circuit that includes an integrated circuit. The test assembly may include structural members that limit movement of components relative to each other.

Abstract: A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of "levels", each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level.