Abstract: A wafer transfer machine transfers wafers from either of a first wafer cassette (55) and a second wafer cassette (56) having incompatible registration features into the other, and includes a support plate (30) having a top surface (38) for supporting the first and second wafer cassette. A first and second registration bosses attached to the top surface extend upward into registration features of the first and second wafer cassette, respectively. A carriage (1) is supported by and movable in opposite directions along a track mechanism (41A,B) that is attached in fixed relationship to the support plate (30). First and second wafer pushing members (10A,B) are supported by the carriage. Each wafer pushing member can be moved to push wafers in one of the wafer cassettes into the other by moving the carriage in one direction or the other.

Abstract: A wafer transfer machine transfers wafers from either of a first wafer cassette (55) and a second wafer cassette (56) having incompatible registration features into the other, and includes a support plate (30) having a top surface (38) for supporting the first and second wafer cassette. A first and second registration bosses attached to the top surface extend upward into registration features of the first and second wafer cassette, respectively. A carriage (1) is supported by and movable in opposite directions along a track mechanism (41A,B) that is attached in fixed relationship to the support plate (30). First and second wafer pushing members (10A,B) are supported by the carriage. Each wafer pushing member can be moved to push wafers in one of the wafer cassettes into the other by moving the carriage in one direction or the other.

Abstract: A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. for a time. The temperature is then increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C.

Abstract: A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. for a time. The temperature is then increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C.