Abstract: Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated therewith, wherein the cantilever vibrates when in the presence of a vibration source, and wherein the harvesting device generates a current upon vibration of the cantilever. The generated current is present at an output. A bias flip circuit is used to tune the resonant frequency of the harvesting device based on measurements of the vibration source that causes the cantilever to vibrate, wherein the bias flip circuit includes a switch that connects and disconnects an inductor to the output.

Abstract: Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated therewith, wherein the cantilever vibrates when in the presence of a vibration source, and wherein the harvesting device generates a current upon vibration of the cantilever. The generated current is present at an output. A bias flip circuit is used to tune the resonant frequency of the harvesting device based on measurements of the vibration source that causes the cantilever to vibrate, wherein the bias flip circuit includes a switch that connects and disconnects an inductor to the output.

Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

Abstract: The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device (100). The device (100) comprises a tensile-strained silicon layer (105) located on a silicon-germanium substrate (110) and silicon-germanium source/drain structures (135, 140) located on or in the tensile-strained silicon layer (105). The PMOS device (100) further includes a channel region (130) located between the silicon-germanium source/drain structures (135, 140) and within the tensile-strained silicon layer (105). The channel region (130) has a compressive stress (145) in a direction parallel to an intended current flow (125) through the channel region (130). Other embodiments of the present invention include a method of manufacturing the PMOS device (200) and a MOS device (300).

Abstract: Signal processing wherein signals are processed using chirp-Z-transform (CZT) techniques and charge transfer device (CTD) transversal filters. The chirp weighting signal may be amplitude modulated to achieve signal apodization and may be generated by impulsing a CTD complex filter having an appropriate impulse response. Signal premultiplication using a one-bit quantized chirp signal is described.Application of these techniques to doppler range processing apparatus wherein radar returns are premultiplied to provide up-chirp multiplied time samples prior to being inputted into a CTD range buffer. Each bit of the CTD has an associated CTD chirp Z-transform complex filter the outputs from each of which are summed and squared. The range bins and the associated complex filters are provided on a common semiconductor chip together with peripheral circuitry.

Abstract: A charge-transfer transversal filter and method of use is provided. In one aspect of the invention a handpass filter is provided where the center frequency of the bandpass is variable responsive to the clock rate applied to the charge-transfer devices. In a different aspect of the invention a matched filter for a chirp signal is provided. The filter requires a minimum number of Nyquist samples by including the provision of a clock rate which varies responsive to the frequency sweep of the input chirp signal. A method for detecting a chirp signal is provided which includes the step of selectively varying the clock rate applied to a charge-transfer shift register responsive to the frequency variations of a selected chirp signal.

Abstract: Circuitry for compensating for charge transfer inefficiency related dispersion in analog charge transfer devices (CTD's) is disclosed. In one aspect of the invention the tap weights of a filter are modified in a preselected manner to provide dispersion correction. In a different configuration, a dispersion compensating filter is connected to the input of a charge transfer delay line to provide an initial signal which is the inverse of the total dispersion of the CTD. In a further aspect of the invention regenerators are inserted into a CTD delay line to provide negative feedback to previous stages of the delay line in order to compensate for dispersion.

Abstract: Signal processing wherein signals are processed using chirp-Z-transform (CZT) techniques and charge transfer device (CTD) transversal filters. The chirp weighting signal may be amplitude modulated to achieve signal apodization and may be generated by impulsing a CTD complex filter having an appropriate impulse response. Signal premultiplication using a one-bit quantized chirp signal is described.Application of these techniques to doppler range processing apparatus wherein radar returns are premultiplied to provide up-chirp multiplied time samples prior to being inputted into a CTD range buffer. Each bit of the CTD has an associated CTD chirp-Z-transform complex filter the outputs from each of which are summed and squared. The range bins and the associated complex filters are provided on a common semiconductor chip together with peripheral circuitry.

Abstract: A variable tap weight convolution filter comprised of charge transfer devices which may be charge coupled devices, bucket brigade devices or a combination of the two, for performing convolutions of an input signal with tap weights from a second input signal, said tap weights varying as a function of time.