Patents by Inventor Dennis Dilley

Dennis Dilley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast internal reference cell trimming for flash EEPROM memory
    Patent number: 5608679
    Abstract: A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a valu
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: March 4, 1997
    Assignee: Intel Corporation
    Inventors: James Q. Mi, Johnny Javanifard, Dennis Dilley
  • Fast internal reference cell trimming for flash EEPROM memory
    Patent number: 5608669
    Abstract: A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a valu
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: March 4, 1997
    Assignee: Intel Corporation
    Inventors: James Q. Mi, Johnny Javanifard, Dennis Dilley