Abstract: A low-power stop mode "snooze" timer is implemented in the processing unit of a communication system, which runs without the use of the usual crystal-controlled oscillator. The "snooze" timer is implemented by a second oscillator with associated timer circuit. The second oscillator runs continually and feeds a timer which is loaded with a suitable value. The timer, when timed out or expired, will reactivate the main processing functions, thus allowing the successful reception of an external signal from a remote transmission source. To compensate for the inaccuracy of the second oscillator due to its dependence upon voltage, process and temperature, the snooze timer's output is calibrated during the wake-up periods against a timing signal derived from the internal crystal-controlled timing source. This calibration compensates for the inherent frequency instability of the second oscillator and allows a timing signal of sufficient accuracy to be maintained over the stop cycle.

Abstract: A method of providing redundancy in an electrically alterable memory divided into addressable blocks within the memory. The electrically alterable memory should have more available blocks than required by the firmware. The method includes the steps of testing the memory to create block status information about good versus bad blocks, writing the block status information into a table in the electrically alterable memory, reordering the table so that contiguous series of entries in the table point only to good blocks, and then providing a block status array comprising block select registers which are initialized with the corresponding ones of the contiguous series of entries so that a nominal address to a bad block is redirected to a good block.