Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: A method of treating psoriasis in a patient previously treated with and determined to be an inadequate responder to an IL-12/23p40 antibody by administering an IL-23 specific antibody, e.g., guselkumab, in a safe and effective amount and the patient achieves PASI75, PASI90, PASI100 or IGA 0 or 1 score as measured 16, 24, 32, 40 and 48 weeks after initial treatment.

Abstract: A method of treating psoriasis in a patient previously treated with and determined to be an inadequate responder to an IL-12/23p40 antibody by administering an IL-23 specific antibody, e.g., guselkumab, in a safe and effective amount and the patient achieves PASI75, PASI90, PASI100 or IGA 0 or 1 score as measured 16, 24, 32, 40 and 48 weeks after initial treatment.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: A method of treating psoriasis in a patient previously treated with and determined to be an inadequate responder to an IL-12/23p40 antibody by administering an IL-23 specific antibody, e.g., guselkumab, in a safe and effective amount and the patient achieves PASI75, PASI90, PASI100 or IGA 0 or 1 score as measured 16, 24, 32, 40 and 48 weeks after initial treatment.

Abstract: A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the computation process. As more data elements become available or are needed, more multiplier-accumulator units are used to perform the necessary multiplication and addition operations. To multiply an N×M matrix by an M×N matrix, the total (maximum) number of used MAC units is “2*N?1”. The number of MAC units used starts with one (1) and increases by two at each computation stage, that is, at the beginning of reading of data elements for each new row of the first matrix. The sequence of the number of MAC units is {1, 3, 5, . . . , 2*N?1} for computation stages each of which corresponds to reading of data elements for each new row of the left hand matrix, also called the first matrix.

Abstract: A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.

Abstract: A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the computation process. As more data elements become available or are needed, more multiplier-accumulator units are used to perform the necessary multiplication and addition operations. To multiply an N×M matrix by an M×N matrix, the total (maximum) number of used MAC units is “2*N?1”. The number of MAC units used starts with one (1) and increases by two at each computation stage, that is, at the beginning of reading of data elements for each new row of the first matrix. The sequence of the number of MAC units is {1, 3, 5, . . . , 2*N?1} for computation stages each of which corresponds to reading of data elements for each new row of the left hand matrix, also called the first matrix.

Abstract: A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.