Patents by Inventor Dennis G. Montierth
Dennis G. Montierth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062798Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.Type: ApplicationFiled: September 14, 2023Publication date: February 22, 2024Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Publication number: 20230420023Abstract: Methods, systems, and devices for a self-refresh state with decreased power consumption are described. A memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. Based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. Additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. In cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Inventors: Shawn M. Hilde, Dennis G. Montierth, Garth N. Grubb
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Patent number: 11798610Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.Type: GrantFiled: June 15, 2021Date of Patent: October 24, 2023Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Patent number: 11670356Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).Type: GrantFiled: July 16, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Yoshinori Fujiwara, Harish V. Gadamsetty, Gary Howe, Dennis G. Montierth, Michael A. Shore, Jason M. Johnson
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Publication number: 20230020753Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshinori Fujiwara, Harish V. Gadamsetty, Gary Howe, Dennis G. Montierth, Michael A. Shore, Jason M. Johnson
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Publication number: 20220382628Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Boon Hor Lam, Karl L. Major, Loon Ming Ho, Dennis G. Montierth
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Patent number: 11475938Abstract: A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.Type: GrantFiled: June 28, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Dennis G. Montierth, Boon Hor Lam, C Omar Benitez
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Patent number: 11456049Abstract: Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.Type: GrantFiled: July 2, 2020Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Jason M. Johnson, Dennis G. Montierth
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Patent number: 11437116Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: April 17, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Patent number: 11416333Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.Type: GrantFiled: August 22, 2019Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Boon Hor Lam, Karl L. Major, Loon Ming Ho, Dennis G. Montierth
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Patent number: 11417383Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.Type: GrantFiled: February 26, 2021Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
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Patent number: 11302374Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.Type: GrantFiled: August 23, 2019Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
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Patent number: 11257566Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.Type: GrantFiled: August 19, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventor: Dennis G. Montierth
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Publication number: 20220005541Abstract: Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Inventors: Jason M. Johnson, Dennis G. Montierth
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Patent number: 11200942Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).Type: GrantFiled: August 23, 2019Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Matthew D. Jenkinson, Jiyun Li, Dennis G. Montierth, Nathaniel J. Meier
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Publication number: 20210327491Abstract: A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Dennis G. Montierth, Boon Hor Lam, C Omar Benitez
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Publication number: 20210304813Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.Type: ApplicationFiled: June 15, 2021Publication date: September 30, 2021Applicant: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Patent number: 11087824Abstract: A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.Type: GrantFiled: January 10, 2020Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Dennis G. Montierth, Boon Hor Lam, C Omar Benitez
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Patent number: 11069393Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.Type: GrantFiled: June 4, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Publication number: 20210217460Abstract: A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: Dennis G. Montierth, Boon Hor Lam, C Omar Benitez