Patents by Inventor Dennis Gates

Dennis Gates has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080034147
    Abstract: A method, system and computer program for transferring packets between devices connected to a PCI-Express bus of a computer. A selected pair of devices, such as for example a root complex device and an endpoint device or a pair of endpoint devices, connected to the PCI-Express bus, are configured to transmit/receive data with their respective maximum payload size (MPS). A packet, such as for example a read completion packet, a write memory packet or a message request packet, can then be transmitted from the source device to the destination device. If the source device MPS exceeds the destination device MPS, the packet can be divided into a plurality of sub-packets. Each of sub packets has a maxmimum payload size based on the MPS of the destination device. The sub-packets can then be transmitted to the destination device so that the packet can be delivered to the destination device.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 7, 2008
    Inventors: Robert Stubbs, John Kloeppner, Dennis Gates
  • Publication number: 20070258300
    Abstract: A method and system for verifying synchronized signals if provided. The method may include receiving a signal from a first clock domain for synchronization. Further, a random number for the received signal may be generated and a reset signal imposed for utilization as a reference point for the received signal delay. In addition, the method may involve retrieving the random number for the received signal when a reset signal is removed. Moreover, the random number may be converted into a random delay value which may then be applied to the received signal.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 8, 2007
    Inventors: Richard Kelderhouse, Thomas Langford, Dennis Gates
  • Publication number: 20070021239
    Abstract: In a gripping device comprising a gripping mechanism including a pair of gripping jaws, normally opened, an actuating mechanism to close the pair of gripping jaws, and an elongate shaft connecting the actuating and gripping mechanisms, each gripping jaw has a gripping end affixed to such gripping jaw and configured to hold a golf tee having a head defining one end, a tip defining an opposite end, and a stem between the head and the tip, so as to allow the tip and an adjacent portion of the stem to remain exposed. Each gripping end has a bearing surface, which bears against the end defined by the head of such a tee being held. Being resilient and being concave, the gripping ends are adapted to hold a golf ball, if a golf tee is not being held. Thus, the gripping device is adapted to enable a golfer to set a golf tee without stooping and to place a golf ball onto a golf tee, which has been set, without stooping. The golf tee may be a standard tee or a “step” tee.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 25, 2007
    Inventor: Dennis Gates
  • Patent number: 6912687
    Abstract: A parity assist circuit that provides multiple XOR calculations using a scatter-gather list is disclosed. The parity assist circuit includes a control circuit that obtains a plurality of source operands in response to a scatter-gather list, and an XOR engine that provides a plurality of XOR products computed from the supplied source operands. Destination and length parameters in the scatter-gather list are used by the XOR engine to store the XOR computation product and to determine the length of the data in the source and destination blocks to be computed. Preferably, the parity assist circuit is part of a RAID controller that includes a processor and a cache memory.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: June 28, 2005
    Assignee: LSI Logic Corporation
    Inventors: Dennis Gates, Rodney A. DeKoning
  • Patent number: 6823472
    Abstract: A shared resource manager circuit for use in conjunction with multiple processors to manage allocation and deallocation of a shared resource. The shared resource manager allocates and deallocates software resources for utilization by the processors in response to allocation and deallocation requests by the processors. The shared resource manager may include a bus arbitrator as required in a particular application for interfacing with a system bus coupled to the processors to provide mutual exclusion in access to the shared resource manager among the multiple processors. The shared resource manager may manage a memory block (FIFO queue) with multiple resource control blocks. A system may advantageously apply a plurality of shared resource managers coupled to a plurality of processors via a common interface bus. Each shared resource manager device may then be associated with management of one particular shared resource.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: November 23, 2004
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, John Kloeppner, Dennis Gates, Keith Holt