Abstract: An recovery circuit is described for recovering data from serially transmitted digital signals wherein a very long hold time and infinite phase range is desired. The recovery circuit includes a variable delay line, a data tracking phase-locked loop (PLL), a clock tracking phase-locked loop, a phase sensor, and a switch. The variable delay line is responsive to a feedback signal and a clock signal for generating a first delayed phase-locked signal. The data tracking phase-locked loop is responsive to the first delayed phase-locked signal and a data signal for producing a data phase error signal. Similarly, the clock tracking phase-locked loop is responsive to the clock signal for providing a second delayed phase-locked signal. Responsive to both of the delayed phase-locked signals is the phase sensor which provides a select output signal when the phase-locked signals are in phase with each other.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.