Patents by Inventor Dennis J. Warner

Dennis J. Warner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus of stress relief in semiconductor structures
    Patent number: 7786007
    Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: August 31, 2010
    Assignee: Infineon Technologies AG
    Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
  • Method and Apparatus of Stress Relief in Semiconductor Structures
    Publication number: 20080213993
    Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
    Type: Application
    Filed: April 7, 2008
    Publication date: September 4, 2008
    Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
  • Method and apparatus of stress relief in semiconductor structures
    Patent number: 7368804
    Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 6, 2008
    Assignee: Infineon Technologies AG
    Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
  • Electrical line end shortening quantification
    Patent number: 6845493
    Abstract: The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a conductor at each end, each conductor connected to a separate contact with the contacts connected by a polysilicon conductor. The conductors can vary in length by a constant increment from conductive path to conductive path, beginning with a length that results in a significant overlap at the contacts to a length that results in a significant underlap at the contacts. Resistance measurements of each conductive path can be made until a change either to or from an “open” occurs; this is the point from which, using the constant increment, the LES can be characterized.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 18, 2005
    Assignee: Infineon Technologies AG
    Inventor: Dennis J. Warner
  • Method and apparatus of stress relief in semiconductor structures
    Publication number: 20040227214
    Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
  • Electrical line end shortening quantification
    Publication number: 20040210859
    Abstract: The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a conductor at each end, each conductor connected to a separate contact with the contacts connected by a polysilicon conductor. The conductors can vary in length by a constant increment from conductive path to conductive path, beginning with a length that results in a significant overlap at the contacts to a length that results in a significant underlap at the contacts. Resistance measurements of each conductive path can be made until a change either to or from an “open” occurs; this is the point from which, using the constant increment, the LES can be characterized.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 21, 2004
    Inventor: Dennis J. Warner