Patents by Inventor Dennis Jeurissen

Dennis Jeurissen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8686779
    Abstract: The invention concerns in general measurement of the transfer function of linear time invariant systems, more particular the calibration of such systems based on a measured transfer function. According to a first aspect the present invention an arrangement for measuring the transfer function of a linear time-invariant system is disclosed. According to a second aspect of the present invention the arrangement is implemented into a linear time-invariant circuitry having a transfer function representing the amplitude and phase characteristic of the circuitry, where by means of the arrangement for measuring the transfer function the transfer function can be optimized in accordance with certain criteria on-the-fly, i.e. in or before operation of the circuit. Finally, an effective and simple method for measuring of the transfer function of a linear time-invariant system together with the use or application of the method is shown.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventors: Dennis Jeurissen, Gerben Willem De Jong, Jan Van Sinderen
  • Patent number: 8680929
    Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 25, 2014
    Assignee: ST-Ericsson S.A.
    Inventors: Gerben W. De Jong, Dennis Jeurissen
  • Patent number: 8660508
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 25, 2014
    Assignee: NXP, B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans
  • Publication number: 20120105128
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Application
    Filed: April 23, 2010
    Publication date: May 3, 2012
    Applicant: NXP B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans
  • Patent number: 8138817
    Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: March 20, 2012
    Assignee: NXP B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Gerben Willem De Jong, Rachid El Waffaoui, Dennis Jeurissen, Jan Van Sinderen, Simon W K Lee
  • Publication number: 20110164666
    Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.
    Type: Application
    Filed: May 21, 2009
    Publication date: July 7, 2011
    Inventors: Gerben W. De Jong, Dennis Jeurissen
  • Publication number: 20110043267
    Abstract: The invention concerns in general measurement of the transfer function of linear time invariant systems, more particular the calibration of such systems based on a measured transfer function. According to a first aspect the present invention an arrangement for measuring the transfer function of a linear time-invariant system is disclosed. According to a second aspect of the present invention the arrangement is implemented into a linear time-invariant circuitry having a transfer function representing the amplitude and phase characteristic of the circuitry, where by means of the arrangement for measuring the transfer function the transfer function can be optimized in accordance with certain criteria on-the-fly, i.e. in or before operation of the circuit. Finally, an effective and simple method for measuring of the transfer function of a linear time-invariant system together with the use or application of the method is shown.
    Type: Application
    Filed: April 30, 2009
    Publication date: February 24, 2011
    Applicant: NXP B.V.
    Inventors: Dennis Jeurissen, Gerben Willem De Jong, Jan Van Sinderen
  • Publication number: 20100253412
    Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
    Type: Application
    Filed: October 29, 2008
    Publication date: October 7, 2010
    Applicant: NXP B.V.
    Inventors: Johannes H.A. Brekelmans, Gerben W. De Jong, Rachid El Waffaoui, Dennis Jeurissen, Jan Van Sinderen, Simon WK Lee