Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.

Abstract: This invention pertains to a method of fabricating an MRAM structure. The method includes forming a pinned layer within a protective region defined by sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: A method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper magnetic layer positioned over it. The method of MRAM fabrication utilizes a spacer processing technique, whereby the upper magnetic layer of the MRAM stack structure is formed between the region defined by the spacers, thereby allowing for self-alignment of the upper magnetic layer over the underlying pinned magnetic layer.

Abstract: A method of making a fuse and a fuse, together with systems and integrated circuits where the fuse provides benefits, are described. A fuse comprising a conductive material is formed on a substrate. A series of dielectric layers having a composite thickness is formed on the substrate and the fuse. The series of dielectric layers serves to insulate a series of conductive layers from each other. The conductive layers are disposed above portions of the substrate. An opening is formed extending through a passivation layer and the series of dielectric layers. The opening exposes a portion of the fuse. Another dielectric layer is formed on the fuse and the fuse may thereafter be programmed by directing a laser beam onto the fuse through the opening.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.