Abstract: A communications switch communicates a message to a particular access network endpoint by forwarding an identification of that endpoint along with the message, link-by-link, through the access network, the forwarding being accomplished by using previously stored routing information identifying, at the switch and at each cross-connection point, a particular downstream link over which the endpoint can ultimately be reached. The links connecting the cross-connection points are multiplexed links supporting digital loop carrier and fiber-in-the-loop communications. The routing information is generated and stored automatically by having each network element report information about itself upstream into the network.

Abstract: A communications switch communicates a message to a particular access network endpoint by forwarding an identification of that endpoint along with the message, link-by-link, through the access network, the forwarding being accomplished by using previously stored routing information identifying, at the switch and at each cross-connection point, a particular downstream link over which the endpoint can ultimately be reached. The links connecting the cross-connection points am time-division-multiplexed links supporting digital loop carrier and fiber-in-the-loop communications. The routing information is generated and stored automatically by having each network element report information about itself upstream into the network.

Abstract: The invention relates to methods and apparatus for regulating traffic in a Broadband Integrated Services Digital Network (B-ISDN). Terminal adapters interface between terminals and the B-ISDN. Whenever a first terminal wishes to transmit a data message to a second terminal, the source adapter, connected to the first terminal, allocates transmit bandwidth for the transmission of the message and sends a request message to a destination adapter, connected to the second terminal, for checking availability of and allocating receive bandwidth. The data message is sent only if bandwidth has been allocated on both ends. Overflow traffic is throttled at the adapters before it enters the network, thereby reducing the number of data cells lost because of the limited storage of the network.

Abstract: A method and apparatus for allocating work requests among a plurality of processors attached to a data ring. Each processor has an interface for communicating with the data ring. The interface for each work request accepting processor has a memory defining a plurality of destination addresses for which the associated processor will accept work requests. Each type of work request has several destination addresses corresponding to different priority levels. If that processor becomes too heavily loaded, it will delete one or more of the destination addresses for which the interface will accept work requests. Such a deletion results in the processor only accepting higher priority requests for a type of work request. Work request generating processors detect work request messages which have not been accepted when they return on the ring. Such messages are then retransmitted at a higher priority, and with a longer delay between consecutive transmissions of the work request message.

Abstract: A switching system including a number of switching modules each having a plurality of access ports. Incoming and outgoing packet channels are extended between each switching module and an inter-module packet switch. Each of the switching modules includes both a packet switching unit and a circuit switching unit for switching information to and from the access ports. Each switching module further includes a control unit that controls the switching units and that generates inter-module control packets, and a communication interface that transmits inter-module control packets generated by the control unit on the incoming packet channel to the inter-module packet switch. The communication interface also transmits inter-module control packets received on the outgoing packet channel from the inter-module packet switch to the control unit.

Abstract: A multiprocessor arrangement in which the individual program functions of a program process are executed on different processors. Data shared by different program functions is stored in shared memory and the programs are stored in local memory of the individual processors. One processor calls for the execution of a program function by another processor by causing the program address and a pointer to the program function context to be loaded into a work queue of the called processor. Input/output modules are treated as processors. Facilities are provided for the transfer of blocks of data over the interconnection bus system. Virtual address are translated to physical addresses in one facility common to all processors.