Abstract: A mixer (20) has a differential transistor pair (22, 24) receiving first and second reference currents at first and second nodes (30, 34). An RF signal drives the differential transistor pair. A first switching circuit (44, 46) is coupled to the first node and a second switching circuit (52, 54) is coupled to the second node. An LO signal drives the first and second switching circuits. The first and second switching circuit each have first and second outputs that are cross-coupled at output nodes (48, 50) to provide a differential IF output current representative of the sum and difference between the frequency of the RF signal and the frequency of the LO signal.

Abstract: An RF mixer (10) provides signal gain in a transconductor block (12). A first transistor (36) is sized M times larger than a second transistor (18) to generate the desired signal gain. The gain of the RF mixer (10) is the value M times an output impedance Z.sub.OUT divided by an input impedance Z.sub.IN. A first current (I.sub.40) conducted by the first transistor (36) is matched to a sum of the second current (I.sub.24) conducted by the second transistor (18) and a third current (I.sub.28). The first current is supplied to a first differential transistor pair (46, 48) and the summed current is supplied to a second differential transistor pair (56, 58) to provide balance in switching circuit (50).

Abstract: A subscriber line interface circuit (SLIC) sets AC and DC output impedances as seen by first and second transmission signals. The common mode variation and differential variation of the first and second transmission signals is AC-sensed to provide a common mode feedback signal and a differential feedback signal which in turn controls the AC output impedance. The DC component of the first and second transmission signals is blocked allowing downstream amplifiers to operate at reduced power supply potentials. The DC variation of the first and second transmission signals is also sensed for providing a DC feedback signal to control the DC output impedance.

Abstract: A transient protection circuit provides protection from high voltage transients appearing along a transmission line by sensing a predetermined threshold of the voltage developed thereon and opening the conduction path through first and second switching circuits in the transmission line. The switching circuits are implemented with first and second serially coupled transistors sharing a common drain and enabled by a control signal during normal operation. The first and second transistors each have a diode oriented to conduct from the source to the drain for bi-directional operation. During high voltage transient conditions, a sensing circuit detect a predetermined threshold of the potential on the transmission line and disables one of the first and second transistors which opens the conduction path through the first and second switching circuits thereby suppressing the surge currents flowing therethrough.

Abstract: A circuit for enhancing the alpha of a transistor. A current supplying circuit passes the base current of the transistor through a first and second current mirror for providing current at the emitter of the transistor such that the apparent emitter current of the transistor is made substantially equal to the collector current of the transistor.

Abstract: A speakerphone circuit having fast sensitive switching between the receive mode and the transmit mode is disclosed which includes circuitry for providing four point sensing at the input and output of both the transmit and receive attenuators located in the transmit and receive signal paths thereof for controlling the gains of the attenuators in a complementary manner. A logic control circuit comprising a controller circuit provides an attenuator algorithm that first detects that voice signals are present in both signal paths then quickly causes the attenuators to be set to equal gains during a fast idle mode to then allow the stronger of the two signals to set the operating mode of the speakerphone.

Abstract: A DC control loop is disclosed which is used in conjunction with a control circuit to precisely set the maximum control voltage produced by the control circuit for maximizing the gain of an attenuator controlled thereby. The attenuator includes a current mirror having an output for sourcing a DC current the magnitude of which is proportional to the gain of the attenuator and the control circuit includes a capacitor that is charged or discharged accordingly to vary the magnitude of the control voltage. The DC control loop includes a circuit for sinking the current supplied from the current mirror and a current of a predetermined magnitude, the circuit being coupled to the output of the current mirror and a transistor which is turned on when the magnitude of the current from the current mirror equals the magnitude of the current sank by the circuit to inhibit further charge or discharge of the capacitor whereby the gain of the attenuator is held at a predetermined maximum value.

Abstract: A control circuit for developing a modulated voltage which is proportional to absolute temperature that includes a thermal current source for producing current having a predetermined temperature coefficient and current steering circuitry for proportionally steering the current between first and second outputs in response to a direct current bias voltage applied thereto wherein the current at the first output of the current steering circuitry flows through a resistor. The resistor is connected between a source of different current operating potential and the first output of the current steering circuitry whereby the voltage developed thereacross due to the current steered therethrough is proportional to absolute temperature.

Abstract: An integrated D flip-flop circuit including a plurality of inverter gates produces an output signal having a frequency that is equal to the frequency of an applied alternating input signal divided by a predetermined divide ratio wherein the improvement comprises an additional inverter gate that has an output connected to a predetermined one of the interconnected inverter gates and is responsive to a divide inhibit signal being applied to an input thereof for changing the divide ratio of the D flip-flop circuit.

Abstract: A sense circuit which senses when the magnitude of a full wave rectified current exceeds a predetermined threshold value comprises current mirrors for diverting a very small portion of the current to an output wherein this current is filtered to produce a direct current (dc) voltage. The magnitude of the dc voltage varies directly with the magnitude of the rectified current. The dc voltage is compared with a reference voltage to produce an output signal when the magnitude of the reference voltage is exceeded.

Abstract: A Class AB amplifier circuit includes bias circuitry for biasing the output transistor into partial conduction independent of the base-to-emitter voltage of the transistor. The bias circuitry is a simple circuit loop including the output transistor and forms the remainder of the amplifier circuit which can be fabricated in monolithic integrated circuit form. The loop comprises a differential amplifier for providing a substantially constant offset voltage across a pair of terminals between which is connected a current biasing component. The current biasing component is connected in series with the output transistor to produce a small quiescent current to flow therethrough, the value of which is independent of the transistor's characteristics.

Abstract: A circuit for limiting the magnitude of current sourced from a first load circuit to a second load circuit to a predetermined value. The circuit includes a current sourcing circuit for sourcing current from the first load circuit to the second and a feedback circuit which is responsive to the magnitude of the current sourced to the second load circuit reaching the predetermined value for supplying any additional current that the second load circuit may require while inhibiting additional current from being sourced from the first load circuit.

Abstract: A balanced multiplier circuit for a subscriber loop interface circuit (SLIC) which provides both loop current to a two-wire bidirectional subscriber loop and suppression of longitudinal signals generated at the two-wire loop input to the SLIC while maintaining the midpoint load voltage at half the available power supply voltage applied to the SLIC.