Abstract: A regenerative amplifier is coupled to a combinational current-steering network to provide a combinational logic and register combination. A differential change in current on the register's input nodes due to current steering is amplified to provide complementary logic values at the output nodes of the register responsive to a clock signal. Various combinational logic functions are implemented by current steering networks. Such a configuration provides the advantages of economy of size, cost and power consumption in the combinational layout because the current steering transistors may be made smaller. Furthermore, such a configuration provides the advantage of decreased set-up time in a registered data path and immunity from external sources of noise via common mode rejection. In one embodiment, a regenerative amplifier includes cross-coupled inverters.

Abstract: A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier stage and a static stage. The amplifier stage has a data input terminal and a clock input terminal. The amplifier stage includes a dual-output amplifier having two output lines connected respectively to two current pulldown paths and a gate connected between the current pulldown paths. The static stage is connected to the amplifier stage and including a static latch.

Abstract: A scannable sense amplifier is provided in which the transfer circuits are implemented using only a pair of NMOS transistors added to column pitched circuits between adjacent sense amplifiers.

Abstract: CMOS logic is coupled to dynamic logic which in turn is coupled to CMOS logic such than a clock is not required for the dynamic logic. Such a mixed static/dynamic buffer provides increased speed and fan-out. A buffer includes a dynamic circuit block coupled between static input and output blocks. The dynamic circuit block receives static true and complement input signals and provides dynamic output control signals responsive thereto. The dynamic circuit block dynamically changes the dynamic output control signals responsive to detecting a transition of the true input signal. The dynamic circuit block does not receive a clock signal. The static output block receives the dynamic output control signals and provides a static output signal responsive thereto. The static input block receives the true input signal and precharges the dynamic circuit block after the dynamic circuit block dynamically changes the dynamic output control signals.

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit.

Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level.

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit.

Abstract: A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array.

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit.

Abstract: A plurality sense amplifiers have first and second internal nodes representing respectively, true and complement values of a latched value. A plurality of transfer circuits are provided with one of the transfer circuits disposed between and coupled to each adjacent pairs of the sense amplifiers. The transfer circuits transfer true and complement values between a previous and a next sense amplifier, thereby providing a scannable sense amplifier.

Abstract: A selective recovery circuit and method for a memory array allows bit line recovery after a write operation on a selective basis so that only those column circuits actually written are recovered to at least non-write voltage levels. For each column circuit within the memory array, a recovery signal generation circuit is provided to determine whether the column circuit was actually written and to generate a recovery signal if the column circuit was written. Each column circuit includes a recovery circuit coupled to the bit line pair which, in response to the recovery signal, restores the voltage level of the bit lines of the column circuit back to an at least non-write voltage level. Other columns which are not actually written by the write operation include those not selected by the column decode circuitry, as well as those selected by the column decode circuitry but which correspond to a non-enabled byte of the data word.

Abstract: A redundancy circuit and method allows replacement of failed memory cells in a semiconductor memory array. Redundancy true and redundancy not comparator circuits are provided in dynamic logic to selectively enable and disable respective redundant row predecode and normal row predecode circuits. In one embodiment, redundancy circuits are row redundancy circuits. As compared with single static row redundancy comparator circuits which are limited by setup time constraints and which degrade access time irrespective of redundant row utilization, a dual dynamic comparator design reduces access time penalties when redundancy is enabled and eliminates access time penalties when redundancy is not required in a particular semiconductor memory array.

Abstract: A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the inverter, and a recovery state for preparing the inverter for the arrival of a new input pulse. The inverter has an extremely fast switching speed because virtually all of the available energy of the input signal is used to set the inverter. The inverter may be used in an inverter chain for rapidly propagating electrical signals.

Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.

Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.

Abstract: An ECL to CMOS translator for BiCMOS circuits. The circuit has a first bipolar transistor which switches the translator from a quiescent state to an active state in the presence of an ECL high level signal. An amplifier driving an NMOS capacitive load amplifies this signal to CMOS levels. Two clock signals reset the circuit to the quiescent state once the ECL high signal has passed. The circuit is kept in the quiescent state by a current source.

Abstract: A synchronous BiCMOS logic circuit which operates between two voltage supplies and has at least one input terminal, an intermediate node and an output terminal is disclosed. The logic circuit is capable of a high speed transition in response to a signal pulse from a first logic state to a second logic state at the input terminal. The logic circuit has at least one MOS input transistor of a first polarity having a gate electrode connected to the input terminal. The MOS input transistor is coupled between the first voltage supply and the output node by its source/drain electrodes. A first current supply connected to the output node to the second voltage supply and weakly holds the intermediate node low when the logic circuit is in an initial state with the MOS input transistor turned off.

Abstract: An imput buffer regenerative latch circuit useful in BiCMOS integrated circuits is presented. The ECL input signal terminal is connected to the base of a bipolar transistor. The emitter of the transistor is connected to one of two input/out nodes of a CMOS regenerative latch circuit by the source/drain path of a MOS transistor. The second input/output node is similar connected to the emitter of a second bipolar transistor by the source/drain path of a second MOS transistor. The base of the second bipolar transistor is held at a reference voltage midway in the ECL voltage range. Latching occurs very quickly when the CMOS latch is activated.

Abstract: An input buffer for converting ECL signals to CMOS signals in a BiCMOS chip. The buffer has an emitter follower circuit for receiving the ECL input signal and is coupled to a static amplifier. The output of the static amplifier is forwarded to a differential amplifier which is activated by a clock signal whenever an ECL high level input is applied to the buffer circuit. The differential voltage output from the differential amplifier represents the CMOS level signal.