Abstract: In a circuit that generates a plurality of dynamic signals in a self-resetting signal path, none of which may occur in some cycles, a handshake circuit generates a signal indicative of whether none of the signals occurred and incorporates the plurality of dynamic signals and the signal indicative that none of the signals occurred into a handshake signal. The handshake circuit generates a "normal operation" signal designating that one of the plurality of dynamic signals occurred. The handshake circuit also generates a "reset" signal indicative that none of the signals occurred.

Abstract: A power-up initialization circuit includes a transistor that generates a positive leakage current at the onset of a power-up ramp voltage. The positive leakage current drives a first node connected to a latch to a first defined state. The latch drives a complementary second node to a second defined state, complementary to the state of the first node. The latch acts as a keeper that is switchable and allows current flow during power-up but prevents leakage current when the power-up is complete and nodes are set to selected states. A keeper is a circuit element that holds a dynamic circuit to a static behavior. One type of keeper is a latch. Another type of keeper is a MOSFET transistor having a thin channel width and a gate terminal connected to a reference such as a ground or VSS reference. A power-up initialization circuit includes a capacitive switch connected to a power source and connected to a power-up control node, and a current source connected to the power source and connected to an internal node.

Abstract: A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows.