Abstract: A symmetrical correlator includes a shift register into which the bit pattern resulting from oversampling a received data signal are clocked using a sample clock. During each cycle of the sample clock, a first number of the bits contained in the shift register are provided to an enable circuit. The enable circuit compares these bits to a predetermined bit pattern and, in response to the correlation therebetween, generates an enabling signal. Also during each cycle of the sample clock, a plurality of bit pairs symmetrical about a predetermined bit position in the shift register are compared for logical equivalency in a plurality of associated logical equivalency circuits. Each of the logic equivalency circuits provides a signal indicative of the logic equivalency of its associated bit pair to an adder.

Abstract: A technique is disclosed for allowing a seamless handover between base stations in a TDMA controller as a telephone handset is transported from one base station's area to another. The disclosed circuitry enables the TDMA controller to assess the quality of the handover before switching to the new base station. When it is determined that a handover operation is to commence, transmissions are made in the original slot time and a handover slot time within the same frame. Also during the same frame, data is received at two separate slot times. Only when it is determined that the data received in the handover slot time contains no transmission errors is the handover completed by then only transmitting on the handover slot transmit time and receiving on the handover slot receive time. In the preferred embodiment, it is determined whether the received data contains no transmission errors by detecting the CRC codes, the signal strength, and the existence of any invalid words.

Abstract: A synchronization method for synchronizing a plurality of base stations in a TDMA communication system is disclosed. The synchronization topology may be via dedicated hardwire, via any DSL from the PSTN, or via an ad-hoc RF synchronization technique. Slots containing data are arranged in frames and these frames are transmitted to the base stations, and received from the base stations, by wireless telephone handsets. Each of the slots in a frame have a guard field comprising a plurality of guard bits. The base stations derive frame sync pulses via the received Unique Word correlation detect. These derived frame sync pulses are ultimately synchronized with frame sync signals received from the master base station.

Abstract: A ROM filter includes a number of ROMs, each of which is programmed to hold data relating to several pulse response curves during only a particular time interval. As data are read into the filter, data pertaining to a particular pulse response curve are addressed in each of the ROMs. The outputs of the ROMs are connected to an adder, which adds the data read from the ROMs and passes it through a digital-to-analog converter. In this arrangement, the ROMs are required to store only the data relating to the pulse response curves during a particular interval. These data are added together in real time in an adder which is external to the ROM. With this structure the area of the ROM can be significantly reduced, as compared with ROM filters in which the addition is programmed into the ROM.