Patents by Inventor Dennis Ma

Dennis Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10333565
    Abstract: A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 25, 2019
    Assignee: Nvidia Corporation
    Inventors: Dennis Ma, Marvin Denman, Eric Tyson, Stephen D. Glaser
  • Patent number: 10200154
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 5, 2019
    Assignee: Nvidia Corporation
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Publication number: 20180278278
    Abstract: A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Inventors: Dennis Ma, Marvin Denman, Eric Tyson, Stephen D. Glaser
  • Patent number: 10003362
    Abstract: A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 19, 2018
    Assignee: Nvidia Corporation
    Inventors: Dennis Ma, Marvin Denman, Eric Tyson, Stephen D. Glaser
  • Patent number: 9954984
    Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 24, 2018
    Assignee: Nvidia Corporation
    Inventors: Dennis Ma, Michael Osborn, Eric Tyson, Stephen D. Glaser, Marvin Denman, Jonathan Owen, Mark Hummel
  • Publication number: 20170288815
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 5, 2017
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Patent number: 9720768
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 1, 2017
    Assignee: Nvidia Corporation
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Patent number: 9690736
    Abstract: A microprocessor within a processing unit is configured to manage to operation of a finite state machine (FSM) that, in turn, manages the operation of a data connector. The FSM may be a hardwired chip component that adheres to a communication protocol associated with the data connector. The microprocessor is configured to execute a software application in order to (i) apply configuration changes to the processing unit during state transitions initiated by the FSM and (ii) cause the FSM to initiate specific state transitions.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: June 27, 2017
    Assignee: NVIDIA Corporation
    Inventors: Dennis Ma, Samuel Vincent
  • Publication number: 20170134054
    Abstract: A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 11, 2017
    Inventors: Dennis Ma, Marvin Denman, Eric Tyson, Stephen D. Glaser
  • Publication number: 20170111144
    Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Dennis Ma, Michael Osborn, Eric Tyson, Stephen D. Glaser, Marvin Denman, Jonathan Owen, Mark Hummel
  • Publication number: 20170097867
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Application
    Filed: October 6, 2015
    Publication date: April 6, 2017
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Patent number: 9390042
    Abstract: A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 12, 2016
    Assignee: NVIDIA Corporation
    Inventors: Wei-Je Huang, Dennis Ma, Hitendra Dutt
  • Publication number: 20140307766
    Abstract: A method includes iteratively scanning, through a processor, at least a portion of a map of equalization coefficients related to channel equalization in a data communication link based on an ordinal integer step size S>1 for N (N>1) different sequences thereof to determine optimal points therein for which a signal quality in the data communication link is optimal. The method also includes performing, through the processor, a fine search for optimal equalization coefficients based on the determined optimal points.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: NVIDIA Corporation
    Inventors: Feroze Karim, Vishal Mehta, Hungse Cha, Hitendra Dutt, Dennis Ma
  • Publication number: 20140019742
    Abstract: A microprocessor within a processing unit is configured to manage to operation of a finite state machine (FSM) that, in turn, manages the operation of a data connector. The FSM may be a hardwired chip component that adheres to a communication protocol associated with the data connector. The microprocessor is configured to execute a software application in order to (i) apply configuration changes to the processing unit during state transitions initiated by the FSM and (ii) cause the FSM to initiate specific state transitions.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Inventors: Dennis Ma, Samuel Vincent
  • Publication number: 20140013023
    Abstract: A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Wei-Je HUANG, Dennis Ma, Hitendra Dutt
  • Patent number: 8532098
    Abstract: A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 10, 2013
    Assignee: Nvidia Corporation
    Inventors: David Reed, Oren Rubinstein, Brad Simeral, Devang Sachdev, Daphne Das, Radha Kanekal, Dennis Ma, Praveen Jain, Manas Mandal
  • Publication number: 20110128963
    Abstract: A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: NVIDIA CORPROATION
    Inventors: David Reed, Oren Rubinstein, Brad Simeral, Devang Sachdev, Daphane Das, Radha Kanekal, Dennis Ma, Praveen Jain, Manas Mandal
  • Publication number: 20070152685
    Abstract: Probe array structures and methods of making probe array structures are disclosed. A plurality of electrically conductive elongate contact structures disposed on a first substrate can be provided. The contact structures can then be partially encased in a securing material such that ends of the contact structures extend from a surface of the securing material. The exposed portions of the contact structures can then be captured in a second substrate.
    Type: Application
    Filed: January 3, 2006
    Publication date: July 5, 2007
    Applicant: FormFactor, Inc.
    Inventors: Benjamin Eldridge, Treliant Fang, John Gritters, Igor Khandros, Dennis Ma, Gaetan Mathieu
  • Publication number: 20050268141
    Abstract: A graphics processing device implementing a set of techniques for power management, preferably at both a subsystem level and a device level, and preferably including peak: power management, a system including a graphics processing device that implements such a set of techniques for power management, and the power management methods performed by such a device or system. In preferred embodiments, the device includes at least two subsystems and hardware mechanisms that automatically seek the lowest power state for the device that does not impact performance of the device or of a system that includes the device. Preferably, the device includes a control unit operable in any selected one of multiple power management modes, and system software can intervene to cause the control unit to operate in any of these modes. For example, the device can include a register interface to which an external processor can write control bits to select among the modes.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 1, 2005
    Inventors: Jonah Alben, Dennis Ma, Brian Kelleher
  • Publication number: 20050231454
    Abstract: A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a microcontroller for use in such a graphics processor or display device. In preferred embodiments, the microcontroller functions as a sequencer for controlling the timing of power up and/or power down operations by one or both of a graphics processor and a display device. The microcontroller is implemented to exclude any capacity to handle interrupts and so can provide guaranteed timing, and is preferably implemented to be small, simple, and programmable, and to store a small number of programs. Each program consists of instructions belonging to a small instruction set, such as a set consisting of set and clear instructions (for overriding or overwriting specified register bits) and wait, release, and stop instructions.
    Type: Application
    Filed: June 20, 2005
    Publication date: October 20, 2005
    Inventors: Jonah Alben, Dennis Ma